28-4 Vol. 3C

VMX SUPPORT FOR ADDRESS TRANSLATION

— Bits 11:3 are bits 38:30 of the guest-physical address.
— Bits 2:0 are all 0.

Because an EPT PDPTE is identified using bits 47:30 of the guest-physical address, it controls access to a 1-GByte 
region of the guest-physical-address space. Use of the EPT PDPTE depends on the value of bit 7 in that entry:

1

•

If bit 7 of the EPT PDPTE is 1, the EPT PDPTE maps a 1-GByte page. The final physical address is computed as 
follows:
— Bits 63:52 are all 0.
— Bits 51:30 are from the EPT PDPTE.
— Bits 29:0 are from the original guest-physical address.
The format of an EPT PDPTE that maps a 1-GByte page is given in Table 28-2.

•

If bit 7 of the EPT PDPTE is 0, a 4-KByte naturally aligned EPT page directory is located at the physical address 
specified in bits 51:12 of the EPT PDPTE. The format of an EPT PDPTE that references an EPT page directory is 
given in Table 28-3.

1. Not all processors allow bit 7 of an EPT PDPTE to be set to 1. Software should read the VMX capability MSR 

IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to determine whether this is allowed.

Table 28-2.  Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page

Bit 

Position(s)

Contents

0

Read access; indicates whether reads are allowed from the 1-GByte page referenced by this entry

1

Write access; indicates whether writes are allowed to the 1-GByte page referenced by this entry

2

Execute access; indicates whether instruction fetches are allowed from the 1-GByte page referenced by this entry

5:3

EPT memory type for this 1-GByte page (see Section 28.2.6)

6

Ignore PAT memory type for this 1-GByte page (see Section 28.2.6)

7

Must be 1 (otherwise, this entry references an EPT page directory)

8

If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 1-GByte page referenced 

by this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0

9

If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 1-GByte page referenced by 

this entry (see Section 28.2.4). Ignored if bit 6 of EPTP is 0

11:10

Ignored

29:12

Reserved (must be 0)

(N–1):30

Physical address of the 1-GByte page referenced by this entry

1

NOTES:

1. N is the physical-address width supported by the logical processor.

51:N

Reserved (must be 0)

62:52

Ignored

63

Suppress #VE. If the “EPT-violation #VE” VM-execution control is 1, EPT violations caused by accesses to this page 

are convertible to virtualization exceptions only if this bit is 0 (see Section 25.5.6.1). If “EPT-violation #VE” VM-

execution control is 0, this bit is ignored.