3-6 Vol. 1

BASIC EXECUTION ENVIRONMENT

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Descriptor table registers — The global descriptor table register (GDTR) and interrupt descriptor table 
register (IDTR) expand to 10 bytes so that they can hold a full 64-bit base address. The local descriptor table 
register (LDTR) and the task register (TR) also expand to hold a full 64-bit base address.

3.3 MEMORY 

ORGANIZATION

The memory that the processor addresses on its bus is called physical memory. Physical memory is organized as 
a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address. The physical 
address space ranges from zero to a maximum of 2

36 

−

 

1 (64 GBytes) if the processor does not support Intel 

64 architecture. Intel 64 architecture introduces a changes in physical and linear address space; these are 
described in Section 3.3.3, Section 3.3.4, and Section 3.3.7.

Figure 3-2.  64-Bit Mode Execution Environment

0

2^64 -1

Sixteen 64-bit

64-bits

64-bits

General-Purpose Registers

Segment Registers

RFLAGS Register
RIP (Instruction Pointer Register)

Address Space

Six 16-bit

Registers

Registers

Eight 80-bit

Registers

Floating-Point

Data Registers

Eight 64-bit

Registers

MMX Registers

XMM Registers

Sixteen 128-bit

Registers

16 bits

Control Register

16 bits

Status Register

64 bits

FPU Instruction Pointer Register

64 bits

FPU Data (Operand) Pointer Register

FPU Registers

MMX Registers

XMM Registers

32-bits

MXCSR Register

Opcode Register (11-bits)

Basic Program Execution Registers

16 bits

Tag Register

Four 128-bit Registers

Bounds Registers

BNDCFGU

BNDSTATUS

YMM Registers

Sixteen 256-bit

Registers

YMM Registers