Vol. 1 3-9

BASIC EXECUTION ENVIRONMENT

3.3.4 

Modes of Operation vs. Memory Model

When writing code for an IA-32 or Intel 64 processor, a programmer needs to know the operating mode the 
processor is going to be in when executing the code and the memory model being used. The relationship between 
operating modes and memory models is as follows:

•

Protected mode — When in protected mode, the processor can use any of the memory models described in 
this section. (The real-addressing mode memory model is ordinarily used only when the processor is in the 
virtual-8086 mode.) The memory model used depends on the design of the operating system or executive. 
When multitasking is implemented, individual tasks can use different memory models.

•

Real-address mode

 

— When in real-address mode, the processor only supports the real-address mode 

memory model.

•

System management mode

 

— When in SMM, the processor switches to a separate address space, called the 

system management RAM (SMRAM). The memory model used to address bytes in this address space is similar 
to the real-address mode model. See Chapter 34, “System Management Mode,” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3C, for more information on the memory model used in 
SMM.

•

Compatibility mode — Software that needs to run in compatibility mode should observe the same memory 
model as those targeted to run in 32-bit protected mode. The effect of segmentation is the same as it is in 32-
bit protected mode semantics.

•

64-bit mode — Segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address 
space. Specifically, the processor treats the segment base of CS, DS, ES, and SS as zero in 64-bit mode (this 
makes a linear address equal an effective address). Segmented and real address modes are not available in 64-
bit mode.

3.3.5 

32-Bit and 16-Bit Address and Operand Sizes

IA-32 processors in protected mode can be configured for 32-bit or 16-bit address and operand sizes. With 32-bit 
address and operand sizes, the maximum linear address or segment offset is FFFFFFFFH (2

32

-1); operand sizes are 

typically 8 bits or 32 bits. With 16-bit address and operand sizes, the maximum linear address or segment offset is 
FFFFH (2

16

-1); operand sizes are typically 8 bits or 16 bits. 

When using 32-bit addressing, a logical address (or far pointer) consists of a 16-bit segment selector and a 32-bit 
offset; when using 16-bit addressing, an address consists of a 16-bit segment selector and a 16-bit offset. 
Instruction prefixes allow temporary overrides of the default address and/or operand sizes from within a program.
When operating in protected mode, the segment descriptor for the currently executing code segment defines the 
default address and operand size. A segment descriptor is a system data structure not normally visible to applica-
tion code. Assembler directives allow the default addressing and operand size to be chosen for a program. The 
assembler and other tools then set up the segment descriptor for the code segment appropriately.
When operating in real-address mode, the default addressing and operand size is 16 bits. An address-size override 
can be used in real-address mode to enable 32-bit addressing. However, the maximum allowable 32-bit linear 
address is still 000FFFFFH (2

20

-1).

3.3.6 

Extended Physical Addressing in Protected Mode

Beginning with P6 family processors, the IA-32 architecture supports addressing of up to 64 GBytes (2

36

 

bytes) of 

physical memory. A program or task could not address locations in this address space directly. Instead, it 
addresses individual linear address spaces of up to 4 GBytes that mapped to 64-GByte physical address space 
through a virtual memory management mechanism. Using this mechanism, an operating system can enable a 
program to switch 4-GByte linear address spaces within 64-GByte physical address space.
The use of extended physical addressing requires the processor to operate in protected mode and the operating 
system to provide a virtual memory management system. See “36-Bit Physical Addressing Using the PAE Paging 
Mechanism” in Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3A.