13-10 Vol. 1

MANAGING STATE USING THE XSAVE FEATURE SET

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Bytes 31:28 are used for the MXCSR_MASK value. XRSTOR and XRSTORS ignore this field.

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Bytes 159:32 are used for x87 state.

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Bytes 287:160 are used for the registers XMM0–XMM7. 

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Bytes 415:288 are used for the registers XMM8–XMM15. These fields are used only in 64-bit mode. Executions 
of XSAVE, XSAVEOPT, XSAVEC, and XSAVES outside 64-bit mode do not modify these bytes; executions of 
XRSTOR and XRSTORS outside 64-bit mode do not update XMM8–XMM15. See Section 13.13.

SSE state is XSAVE-managed but the SSE feature is not XSAVE-enabled. The XSAVE feature set can operate on SSE 
state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage SSE state 
(XCR0[1] = 1). Software can otherwise use SSE state even if the XSAVE feature set is not enabled or has not been 
configured to manage SSE state.

13.5.3 AVX 

State

The register state used by the Intel

®

 Advanced Vector Extensions (AVX) comprises the MXCSR register and 16 256-

bit vector registers called YMM0–YMM15. The low 128 bits of each register YMMi is identical to the SSE register 
XMMi. Thus, the new state register state added by AVX comprises the upper 128 bits of the registers YMM0–
YMM15. These 16 128-bit values are denoted YMM0_H–YMM15_H and are collectively called AVX state.
As noted in Section 13.1, the XSAVE feature set manages AVX state as user state component 2. Thus, AVX state is 
located in the extended region of the XSAVE area (see Section 13.4.3).
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=2):EBX enumerates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of the XSAVE area used for AVX state (when the standard format 
of the extended region is used). CPUID.(EAX=0DH,ECX=2):EAX enumerates the size (in bytes) required for AVX 
state.
The XSAVE feature set partitions YMM0_H–YMM15_H in a manner similar to that used for the XMM registers (see 
Section 13.5.2). Bytes 127:0 of the AVX-state section are used for YMM0_H–YMM7_H. Bytes 255:128 are used for 
YMM8_H–YMM15_H, but they are used only in 64-bit mode. Executions of XSAVE, XSAVEOPT, XSAVEC, and 
XSAVES outside 64-bit mode do not modify bytes 255:128; executions of XRSTOR and XRSTORS outside 64-bit 
mode do not update YMM8_H–YMM15_H. See Section 13.13. In general, bytes 16i+15:16i are used for YMMi_H 
(for 0 ≤ i ≤ 15).
AVX state is XSAVE-managed and the AVX feature is XSAVE-enabled. The XSAVE feature set can operate on AVX 
state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage AVX state 
(XCR0[2] = 1). AVX instructions cannot be used unless the XSAVE feature set is enabled and has been configured 
to manage AVX state.

13.5.4 MPX 

State

The register state used by the Intel

®

 Memory Protection Extensions (MPX) comprises the 4 128-bit bounds regis-

ters BND0–BND3 (BNDREG state); and the 64-bit user-mode configuration register BNDCFGU and the 64-bit MPX 
status register BNDSTATUS (collectively, BNDCSR state). Together, these two user state components compose 
MPX state.
As noted in Section 13.1, the XSAVE feature set manages MPX state as state components 3–4. Thus, MPX state is 
located in the extended region of the XSAVE area (see Section 13.4.3). The following items detail how these state 
components are organized in this region:

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BNDREG state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=3):EBX enumerates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of the XSAVE area used for BNDREG state (when the 
standard format of the extended region is used). CPUID.(EAX=0DH,ECX=5):EAX enumerates the size (in 
bytes) required for BNDREG state. The BNDREG section is used for the 4 128-bit bound registers BND0–BND3, 
with bytes 16i+15:16i being used for BNDi.

2. While MXCSR and MXCSR_MASK are part of SSE state, their treatment by the XSAVE feature set is not the same as that of the XMM 

registers. See Section 13.7 through Section 13.11 for details.