13-14 Vol. 1

MANAGING STATE USING THE XSAVE FEATURE SET

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PT state. PT state is in its initial configuration if each of the 9 MSRs is 0.

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PKRU state. PKRU state is in its initial configuration if the value of the PKRU is 0.

13.7 

OPERATION OF XSAVE

The XSAVE instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair 
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction 
mask. The logical-AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of the user 
state components to be saved.
The following conditions cause execution of the XSAVE instruction to generate a fault:

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If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.

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If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.

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If the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP) occurs.

1

If none of these conditions cause a fault, execution of XSAVE reads the XSTATE_BV field of the XSAVE header (see 
Section 13.4.2) and writes it back to memory, setting XSTATE_BV[i] (0 ≤ i ≤ 63) as follows:

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If RFBM[i] =  0,  XSTATE_BV[i] is not changed.

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If RFBM[i] =  1,  XSTATE_BV[i] is set to the value of XINUSE[i]. Section 13.6 defines XINUSE to describe the 
processor init optimization and specifies the initial configuration of each state component. The nature of that 
optimization implies the following:
— If state component i is in its initial configuration, XINUSE[i] may be either 0 or 1, and XSTATE_BV[i] may be 

written with either 0 or 1.
XINUSE[1] pertains only to the state of the XMM registers and not to MXCSR. Thus, XSTATE_BV[1] may be 
written with 0 even if MXCSR does not have its RESET value of 1F80H.

— If state component i is not in its initial configuration, XINUSE[i] =  1  and  XSTATE_BV[i] is written with 1.
(As explained in Section 13.6, the initial configurations of some state components may depend on whether the 
processor is in 64-bit mode.)

The XSAVE instruction does not write any part of the XSAVE header other than the XSTATE_BV field; in particular, 
it does not write to the XCOMP_BV field.
Execution of XSAVE saves into the XSAVE area those state components corresponding to bits that are set in RFBM. 
State components 0 and 1 are located in the legacy region of the XSAVE area (see Section 13.4.1). Each state 
component i, 2 ≤ i ≤ 62, is located in the extended region; the XSAVE instruction always uses the standard format 

for the extended region (see Section 13.4.3).
The MXCSR register and MXCSR_MASK are part of SSE state (see Section 13.5.2) and are thus associated with 
RFBM[1]. However, the XSAVE instruction also saves these values when RFBM[2] = 1 (even if RFBM[1] = 0).
See Section 13.5 for specifics for each state component and for details regarding mode-specific operation and 
operation determined by instruction prefixes. See Section 13.13 for details regarding faults caused by memory 
accesses.

13.8 

OPERATION OF XRSTOR

The XRSTOR instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair 
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction 
mask. The logical-AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of the user 
state components to be restored.
The following conditions cause execution of the XRSTOR instruction to generate a fault:

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If the XSAVE feature set is not enabled (CR4.OSXSAVE = 0), an invalid-opcode exception (#UD) occurs.

1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.