Vol. 1 10-3

PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)

address memory). The general-purpose registers are also used to hold operands for some SSE instructions and 
are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.

•

EFLAGS register — This 32-bit register (see Figure 3-8) is used to record result of some compare operations.

10.2.1 

SSE in 64-Bit Mode and Compatibility Mode

In compatibility mode, SSE extensions function like they do in protected mode. In 64-bit mode, eight additional 
XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are 
specified using the ModR/M, SIB encoding described in Section 3.7.5.
Some SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 64-
bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.

10.2.2 XMM 

Registers

Eight 128-bit XMM data registers were introduced into the IA-32 architecture with SSE extensions (see 
Figure 10-2). These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed 
independently from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased 
to any other of the processor’s registers). 

SSE instructions use the XMM registers only to operate on packed single-precision floating-point operands. SSE2 
extensions expand the functions of the XMM registers to operand on packed or scalar double-precision floating-
point operands and packed integer operands (see Section 11.2, “SSE2 Programming Environment,” and Section 
12.1, “Programming Environment and Data types”).
XMM registers can only be used to perform calculations on data; they cannot be used to address memory. 
Addressing memory is accomplished by using the general-purpose registers.
Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit incre-
ments. When storing the entire contents of an XMM register in memory (128-bit store), the data is stored in 16 
consecutive bytes, with the low-order byte of the register being stored in the first byte in memory.

10.2.3 

MXCSR Control and Status Register

The 32-bit MXCSR register (see Figure 10-3) contains control and status information for SSE, SSE2, and SSE3 
SIMD floating-point operations. This register contains: 

•

flag and mask bits for SIMD floating-point exceptions

•

rounding control field for SIMD floating-point operations

Figure 10-2.  XMM Registers

XMM7

XMM6

XMM5

XMM4

XMM3

XMM2

XMM1

XMM0

127

0