Vol. 1 8-25

PROGRAMMING WITH THE X87 FPU

NOTES

When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible 
(under unusual circumstances) for a non-waiting instruction to be interrupted prior to being 
executed to handle a pending x87 FPU exception. The circumstances where this can happen and 
the resulting action of the processor are described in Section D.2.1.3, “No-Wait x87 FPU Instruc-
tions Can Get x87 FPU Interrupt in Window.” 
When operating a P6 family, Pentium 4, or Intel Xeon processor in MS-DOS compatibility mode, 
non-waiting instructions can not be interrupted in this way (see Section D.2.2, “MS-DOS* Compat-
ibility Sub-mode in the P6 Family and Pentium® 4 Processors”).

8.3.13 

Unsupported x87 FPU Instructions

The Intel 8087 instructions FENI and FDISI and the Intel 287 math coprocessor instruction FSETPM perform no 
function in the Intel 387 math coprocessor and later IA-32 processors. If these opcodes are detected in the instruc-
tion stream, the x87 FPU performs no specific operation and no internal x87 FPU states are affected.

8.4 

X87 FPU FLOATING-POINT EXCEPTION HANDLING

The x87 FPU detects the six classes of exception conditions described in Section 4.9, “Overview of Floating-Point 
Exceptions”:

•

Invalid operation (#I), with two subclasses:
— Stack overflow or underflow (#IS)
— Invalid arithmetic operation (#IA)

•

Denormalized operand (#D)

•

Divide-by-zero (#Z)

•

Numeric overflow (#O)

•

Numeric underflow (#U)

•

Inexact result (precision) (#P)

Each of the six exception classes has a corresponding flag bit in the x87 FPU status word and a mask bit in the x87 
FPU control word (see Section 8.1.3, “x87 FPU Status Register,” and Section 8.1.5, “x87 FPU Control Word,” respec-
tively). In addition, the exception summary (ES) flag in the status word indicates when one or more unmasked 
exceptions has been detected. The stack fault (SF) flag (also in the status word) distinguishes between the two 
types of invalid-operation exceptions.
The mask bits can be set with FLDCW, FRSTOR, or FXRSTOR; they can be read with either FSTCW/FNSTCW, 
FSAVE/FNSAVE, or FXSAVE. The flag bits can be read with the FSTSW/FNSTSW, FSAVE/FNSAVE, or FXSAVE 
instruction.

NOTE

Section 4.9.1, “Floating-Point Exception Conditions,” provides a general overview of how the IA-32 
processor detects and handles the various classes of floating-point exceptions. This information 
pertains to x87 FPU as well as SSE/SSE2/SSE3 extensions. 

The following sections give specific information about how the x87 FPU handles floating-point exceptions that are 
unique to the x87 FPU.

8.4.1 

Arithmetic vs. Non-arithmetic Instructions

When dealing with floating-point exceptions, it is useful to distinguish between arithmetic instructions and non-
arithmetic instructions. Non-arithmetic instructions have no operands or do not make substantial changes to 
their operands. Arithmetic instructions do make significant changes to their operands; in particular, they make 
changes that could result in floating-point exceptions being signaled. Table 8-9 lists the non-arithmetic and arith-