Vol. 1 D-5

GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS

In the circuit in Figure D-1, when the x87 FPU exception handler accesses I/O port 0F0H it clears the IRQ13 inter-
rupt request output from Flip Flop #1 and also clocks out the IGNNE# signal (active) from Flip Flop #2. So the 
handler can activate IGNNE#, if needed, by doing this 0F0H access before clearing the x87 FPU exception condition 
(which de-asserts FERR#). 
However, the circuit does not depend on the order of actions by the x87 FPU exception handler to guarantee the 
correct hardware state upon exit from the handler. Flip Flop #2, which drives IGNNE# to the processor, has its 
CLEAR input attached to the inverted FERR#. This ensures that IGNNE# can never be active when FERR# is inac-
tive. So if the handler clears the x87 FPU exception condition before the 0F0H access, IGNNE# does not get acti-
vated and left on after exit from the handler.

D.2.1.3  

No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window

The Pentium and Intel486 processors implement the “no-wait” floating-point instructions (FNINIT, FNCLEX, 
FNSTENV, FNSAVE, FNSTSW, FNSTCW, FNENI, FNDISI or FNSETPM) in the MS-DOS compatibility mode in the 
following manner. (See Section 8.3.11, “x87 FPU Control Instructions,” and Section 8.3.12, “Waiting vs. Non-
waiting Instructions,” for a discussion of the no-wait instructions.)
If an unmasked numeric exception is pending from a preceding x87 FPU instruction, a member of the no-wait class 
of instructions will, at the beginning of its execution, assert the FERR# pin in response to that exception just like 
other x87 FPU instructions, but then, unlike the other x87 FPU instructions, FERR# will be de-asserted. This de-
assertion was implemented to allow the no-wait class of instructions to proceed without an interrupt due to any 
pending numeric exception. However, the brief assertion of FERR# is sufficient to latch the x87 FPU exception 
request into most hardware interface implementations (including Intel’s recommended circuit). 
All the x87 FPU instructions are implemented such that during their execution, there is a window in which the 
processor will sample and accept external interrupts. If there is a pending interrupt, the processor services the 
interrupt first before resuming the execution of the instruction. Consequently, it is possible that the no-wait 
floating-point instruction may accept the external interrupt caused by it’s own assertion of the FERR# pin in the 
event of a pending unmasked numeric exception, which is not an explicitly documented behavior of a no-wait 
instruction. This process is illustrated in Figure D-3.

Figure D-2.  Behavior of Signals During x87 FPU Exception Handling

0F0H Address
   Decode