Vol. 1 8-5

PROGRAMMING WITH THE X87 FPU

The C2 condition code flag is used by the FPREM and FPREM1 instructions to indicate an incomplete reduction (or 
partial remainder). When a successful reduction has been completed, the C0, C3, and C1 condition code flags are 
set to the three least-significant bits of the quotient (Q2, Q1, and Q0, respectively). See “FPREM1—Partial 
Remainder” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2A, for more information on how these instructions use the condition code flags.
The FPTAN, FSIN, FCOS, and FSINCOS instructions set the C2 flag to 1 to indicate that the source operand is 
beyond the allowable range of ±2

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 and clear the C2 flag if the source operand is within the allowable range.

Where the state of the condition code flags are listed as undefined in Table 8-1, do not rely on any specific value in 
these flags.

8.1.3.3  

x87 FPU Floating-Point Exception Flags

The six x87 FPU floating-point exception flags (bits 0 through 5) of the x87 FPU status word indicate that one or 
more floating-point exceptions have been detected since the bits were last cleared. The individual exception flags 
(IE, DE, ZE, OE, UE, and PE) are described in detail in Section 8.4, “x87 FPU Floating-Point Exception Handling.” 
Each of the exception flags can be masked by an exception mask bit in the x87 FPU control word (see Section 8.1.5, 
“x87 FPU Control Word”). The exception summary status flag (ES, bit 7) is set when any of the unmasked exception 
flags are set. When the ES flag is set, the x87 FPU exception handler is invoked, using one of the techniques 
described in Section 8.7, “Handling x87 FPU Exceptions in Software.” (Note that if an exception flag is masked, the 
x87 FPU will still set the appropriate flag if the associated exception occurs, but it will not set the ES flag.) 
The exception flags are “sticky” bits (once set, they remain set until explicitly cleared). They can be cleared by 
executing the FCLEX/FNCLEX (clear exceptions) instructions, by reinitializing the x87 FPU with the FINIT/FNINIT or 
FSAVE/FNSAVE instructions, or by overwriting the flags with an FRSTOR or FLDENV instruction.
The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of the ES flag.

Table 8-1.  Condition Code Interpretation

Instruction

C0

C3

C2

C1

FCOM, FCOMP, FCOMPP, FICOM, FICOMP, FTST, 

FUCOM, FUCOMP, FUCOMPP 

Result of Comparison

Operands 

are not 

Comparable

0 or #IS

FCOMI, FCOMIP, FUCOMI, FUCOMIP

Undefined. (These instructions set the 

status flags in the EFLAGS register.)

#IS

FXAM

 Operand class

Sign

FPREM, FPREM1

Q2

Q1

0 = reduction 

complete
1 = reduction 

incomplete

Q0 or #IS

F2XM1, FADD, FADDP, FBSTP, FCMOVcc, 

FIADD, FDIV, FDIVP, FDIVR, FDIVRP, FIDIV, 

FIDIVR, FIMUL, FIST, FISTP, FISUB, 

FISUBR,FMUL, FMULP, FPATAN, FRNDINT, 

FSCALE, FST, FSTP, FSUB, FSUBP, FSUBR, 

FSUBRP,FSQRT, FYL2X, FYL2XP1

Undefined

Roundup or #IS

FCOS, FSIN, FSINCOS, FPTAN

Undefined

0 = source 

operand within 

range

1 = source 

operand out of 

range

Roundup or #IS 

(Undefined if C2 = 

1)

FABS, FBLD, FCHS, FDECSTP, FILD, FINCSTP, 

FLD, Load Constants, FSTP (ext. prec.), FXCH, 

FXTRACT 

Undefined

0 or #IS