4-20 Vol. 1

DATA TYPES

Software Developer’s Manual, Volumes 3A & 3B, list the floating-point exceptions that can be signaled for each 
floating-point instruction.

4.9.1.1  

Invalid Operation Exception (#I)

The processor reports an invalid operation exception in response to one or more invalid arithmetic operands. If the 
invalid operation exception is masked, the processor sets the IE flag and returns an indefinite value or a QNaN. This 
value overwrites the destination register specified by the instruction. If the invalid operation exception is not 
masked, the IE flag is set, a software exception handler is invoked, and the operands remain unaltered.
See Section 4.8.3.6, “Using SNaNs and QNaNs in Applications,” for information about the result returned when an 
exception is caused by an SNaN.
The processor can detect a variety of invalid arithmetic operations that can be coded in a program. These opera-
tions generally indicate a programming error, such as dividing ∞ by ∞ . See the following sections for information 

regarding the invalid-operation exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:

•

x87 FPU; Section 8.5.1, “Invalid Operation Exception”

•

SIMD floating-point exceptions; Section 11.5.2.1, “Invalid Operation Exception (#I)”

4.9.1.2  

Denormal Operand Exception (#D)

The processor reports the denormal-operand exception if an arithmetic instruction attempts to operate on a 
denormal operand (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”). When the exception is 
masked, the processor sets the DE flag and proceeds with the instruction. Operating on denormal numbers will 
produce results at least as good as, and often better than, what can be obtained when denormal numbers are 
flushed to zero. Programmers can mask this exception so that a computation may proceed, then analyze any loss 
of accuracy when the final result is delivered.
When a denormal-operand exception is not masked, the DE flag is set, a software exception handler is invoked, and 
the operands remain unaltered. When denormal operands have reduced significance due to loss of low-order bits, 
it may be advisable to not operate on them. Precluding denormal operands from computations can be accom-
plished by an exception handler that responds to unmasked denormal-operand exceptions.
See the following sections for information regarding the denormal-operand exception when detected while 
executing x87 FPU or SSE/SSE2/SSE3 instructions:

•

x87 FPU; Section 8.5.2, “Denormal Operand Exception (#D)”

•

SIMD floating-point exceptions; Section 11.5.2.2, “Denormal-Operand Exception (#D)”

4.9.1.3  

Divide-By-Zero Exception (#Z)

The processor reports the floating-point divide-by-zero exception whenever an instruction attempts to divide a 
finite non-zero operand by 0. The masked response for the divide-by-zero exception is to set the ZE flag and return 
an infinity signed with the exclusive OR of the sign of the operands. If the divide-by-zero exception is not masked, 
the ZE flag is set, a software exception handler is invoked, and the operands remain unaltered.
See the following sections for information regarding the divide-by-zero exception when detected while executing 
x87 FPU or SSE/SSE2 instructions:

•

x87 FPU; Section 8.5.3, “Divide-By-Zero Exception (#Z)”

•

SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception (#Z)”

4.9.1.4  

Numeric Overflow Exception (#O)

The processor reports a floating-point numeric overflow exception whenever the rounded result of an instruction 
exceeds the largest allowable finite value that will fit into the destination operand. Table 4-9 shows the threshold 
range for numeric overflow for each of the floating-point formats; overflow occurs when a rounded result falls at or 
outside this threshold range.