Vol. 1 11-15

PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)

Normally, when one or more of the source operands are QNaNs (and neither is an SNaN or in an unsupported 
format), an invalid-operation exception is not generated. The following instructions are exceptions to this rule: the 
COMISS and COMISD instructions; and the CMPPS, CMPSS, CMPPD, and CMPSD instructions (when the predicate 
is less than, less-than or equal, not less-than, or not less-than or equal). With these instructions, a QNaN source 
operand will generate an invalid-operation exception.
The invalid-operation exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode.

11.5.2.2   Denormal-Operand Exception (#D)

The processor signals the denormal-operand exception if an arithmetic instruction attempts to operate on a 
denormal operand. The flag (DE) and mask (DM) bits for the denormal-operand exception are bits 1 and 8, respec-
tively, in the MXCSR register.
The CVTPI2PD, CVTPD2PI, CVTTPD2PI, CVTDQ2PD, CVTPD2DQ, CVTTPD2DQ, CVTSI2SD, CVTSD2SI, CVTTSD2SI, 
CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSS2SI, CVTTSS2SI, CVTSI2SS, CVTDQ2PS, CVTPS2DQ, and CVTTPS2DQ 
conversion instructions do not signal denormal exceptions. The RCPSS, RCPPS, RSQRTSS, and RSQRTPS instruc-
tions do not signal any kind of floating-point exception.
The denormals-are-zero flag (bit 6) of the MXCSR register provides an additional option for handling denormal-
operand exceptions. When this flag is set, denormal source operands are automatically converted to zeros with the 
sign of the source operand (see Section 10.2.3.4, “Denormals-Are-Zeros”). The denormal operand exception is not 
affected by the flush-to-zero mode.
See Section 4.9.1.2, “Denormal Operand Exception (#D),” for more information about the denormal exception. 
See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling unmasked 
exceptions.

11.5.2.3   Divide-By-Zero Exception (#Z)

The processor reports a divide-by-zero exception when a DIVPS, DIVSS, DIVPD or DIVSD instruction attempts to 
divide a finite non-zero operand by 0. The flag (ZE) and mask (ZM) bits for the divide-by-zero exception are bits 2 
and 9, respectively, in the MXCSR register.
See Section 4.9.1.3, “Divide-By-Zero Exception (#Z),” for more information about the divide-by-zero exception. 
See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling unmasked 
exceptions.
The divide-by-zero exception is not affected by the flush-to-zero mode at a single-instruction boundary.
While DAZ does not affect the rules for signaling IEEE exceptions, operations on denormal inputs might have 
different results when DAZ=1. As a consequence, DAZ can have an effect on the floating-point exceptions - 
including the divide-by-zero exception - when observed for a given operation involving denormal inputs.

11.5.2.4   Numeric Overflow Exception (#O)

The processor reports a numeric overflow exception whenever the rounded result of an arithmetic instruction 
exceeds the largest allowable finite value that fits in the destination operand. This exception can be generated with 
the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD, DIVPS, 
DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HSUBPD and HSUBPS 
instructions. The flag (OE) and mask (OM) bits for the numeric overflow exception are bits 3 and 10, respectively, 
in the MXCSR register.
See Section 4.9.1.4, “Numeric Overflow Exception (#O),” for more information about the numeric-overflow excep-
tion. See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling 
unmasked exceptions.
The numeric overflow exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode.