Vol. 3B 19-123
PERFORMANCE-MONITORING EVENTS
24H
Com-
bined
mask
from
and
L2_LINES_IN.
(Core, Prefetch)
L2 cache misses.
This event counts the number of cache lines allocated in the
L2 cache. Cache lines are allocated in the L2 cache as a
result of requests from the L1 data and instruction caches
and the L2 hardware prefetchers to cache lines that are
missing in the L2 cache.
This event can count occurrences for this core or both cores.
It can also count demand requests and L2 hardware
prefetch requests together or separately.
25
H
See
L2_M_LINES_IN.
(Core)
L2 cache line
modifications.
This event counts whenever a modified cache line is written
back from the L1 data cache to the L2 cache.
This event can count occurrences for this core or both cores.
26
H
See
and
L2_LINES_OUT.
(Core, Prefetch)
L2 cache lines evicted. This event counts the number of L2 cache lines evicted.
This event can count occurrences for this core or both cores.
It can also count evictions due to demand requests and L2
hardware prefetch requests together or separately.
27
H
See
and
L2_M_LINES_OUT.(Core,
Prefetch)
Modified lines evicted
from the L2 cache.
This event counts the number of L2 modified cache lines
evicted. These lines are written back to memory unless they
also exist in a modified-state in one of the L1 data caches.
This event can count occurrences for this core or both cores.
It can also count evictions due to demand requests and L2
hardware prefetch requests together or separately.
28
H
Com-
bined
mask
from
and
L2_IFETCH.(Core, Cache
Line State)
L2 cacheable
instruction fetch
requests.
This event counts the number of instruction cache line
requests from the IFU. It does not include fetch requests
from uncacheable memory. It does not include ITLB miss
accesses.
This event can count occurrences for this core or both cores.
It can also count accesses to cache lines at different MESI
states.
29
H
Combin
ed mask
from
18-2,
18-4,
and
L2_LD.(Core, Prefetch,
Cache Line State)
L2 cache reads.
This event counts L2 cache read requests coming from the
L1 data cache and L2 prefetchers.
The event can count occurrences:
• For this core or both cores.
• Due to demand requests and L2 hardware prefetch
requests together or separately.
• Of accesses to cache lines at different MESI states.
2A
H
See
and
L2_ST.(Core, Cache Line
State)
L2 store requests.
This event counts all store operations that miss the L1 data
cache and request the data from the L2 cache.
The event can count occurrences for this core or both cores.
It can also count accesses to cache lines at different MESI
states.
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
Description and
Comment