17-56 Vol. 3B

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

— CPUID.(EAX=10H, ECX=ResID=1):EAX[4:0] reports the length of the capacity bitmask length using 

minus-one notation, i.e. a value of 15 corresponds to the capability bitmask having length of 16 bits. Bits 
31:5 of EAX are reserved.

— CPUID.(EAX=10H, ECX=1):EBX[31:0] reports a bit mask. Each set bit within the length of the CBM 

indicates the corresponding unit of the L3 allocation may be used by other entities in the platform (e.g. an 
integrated graphics engine or hardware units outside the processor core and have direct access to L3). Each 
cleared bit within the length of the CBM indicates the corresponding allocation unit can be configured to 
implement a priority-based allocation scheme chosen by an OS/VMM without interference with other 
hardware agents in the system. Bits outside the length of the CBM are reserved.

— CPUID.(EAX=10H, ECX=1):ECX.CDP[bit 2]: If 1, indicates Code and Data Prioritization Technology is 

supported (see Section 17.17.4). Other bits of CPUID.(EAX=10H, ECX=1):ECX are reserved.

— CPUID.(EAX=10H, ECX=1):EDX[15:0] reports the maximum COS supported for the resource (COS are 

zero-referenced, meaning a reported value of '15' would indicate 16 total supported COS). Bits 31:16 are 
reserved.

•

CAT capability for L2 is enumerated by CPUID.(EAX=10H, ECX=2H), see Figure 17-33. The specific CAT 
capabilities reported by CPUID.(EAX=10H, ECX=2) are:

— CPUID.(EAX=10H, ECX=ResID=2):EAX[4:0] reports the length of the capacity bitmask length using 

minus-one notation, i.e. a value of 15 corresponds to the capability bitmask having length of 16 bits. Bits 
31:5 of EAX are reserved.

— CPUID.(EAX=10H, ECX=2):EBX[31:0] reports a bit mask. Each set bit within the length of the CBM 

indicates the corresponding unit of the L2 allocation may be used by other entities in the platform. Each 
cleared bit within the length of the CBM indicates the corresponding allocation unit can be configured to 
implement a priority-based allocation scheme chosen by an OS/VMM without interference with other 
hardware agents in the system. Bits outside the length of the CBM are reserved.

— CPUID.(EAX=10H, ECX=2):ECX: reserved.
— CPUID.(EAX=10H, ECX=2):EDX[15:0] reports the maximum COS supported for the resource (COS are 

zero-referenced, meaning a reported value of '15' would indicate 16 total supported COS). Bits 31:16 are 
reserved.

A note on migration of Classes of Service (COS): Software should minimize migrations of COS across logical 
processors (across threads or cores), as a reduction in the performance of the Cache Allocation Technology feature 
may result if COS are migrated frequently. This is aligned with the industry-standard practice of minimizing unnec-
essary thread migrations across processor cores in order to avoid excessive time spent warming up processor 

Figure 17-33.  L2 Cache Allocation Technology 

0

16

31

CPUID.(EAX=10H, ECX=ResID=2) Output: 

EDX

ECX

0

31

Reserved

15

EBX

0

31

Bitmask of Shareable Resource with Other executing entities

Reserved

COS_MAX

0

5

31

EAX

4

Reserved

CBM_LEN