10-20 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
101 (INIT Level De-assert)
(Not supported in the Pentium 4 and Intel Xeon processors.) Sends a syn-
chronization message to all the local APICs in the system to set their arbi-
tration IDs (stored in their Arb ID registers) to the values of their APIC IDs
(see Section 10.7, “System and APIC Bus Arbitration”). For this delivery
mode, the level flag must be set to 0 and trigger mode flag to 1. This IPI is
sent to all processors, regardless of the value in the destination field or the
destination shorthand field; however, software should specify the “all in-
cluding self” shorthand.
110 (Start-Up)
Sends a special “start-up” IPI (called a SIPI) to the target processor or
processors. The vector typically points to a start-up routine that is part of
the BIOS boot-strap code (see Section 8.4, “Multiple-Processor (MP) Ini-
tialization”). IPIs sent with this delivery mode are not automatically retried
if the source APIC is unable to deliver it. It is up to the software to deter-
mine if the SIPI was not successfully delivered and to reissue the SIPI if
necessary.
Destination Mode Selects either physical (0) or logical (1) destination mode (see Section 10.6.2, “Determining
Delivery Status (Read Only)
Indicates the IPI delivery status, as follows:
0 (Idle)
Indicates that this local APIC has completed sending any previous IPIs.
1 (Send Pending)
Indicates that this local APIC has not completed sending the last IPI.
Level
For the INIT level de-assert delivery mode this flag must be set to 0; for all other delivery
modes it must be set to 1. (This flag has no meaning in Pentium 4 and Intel Xeon processors,
and will always be issued as a 1.)
Trigger Mode
Selects the trigger mode when using the INIT level de-assert delivery mode: edge (0) or level
(1). It is ignored for all other delivery modes. (This flag has no meaning in Pentium 4 and Intel
Xeon processors, and will always be issued as a 0.)
Destination Shorthand
Indicates whether a shorthand notation is used to specify the destination of the interrupt and,
if so, which shorthand is used. Destination shorthands are used in place of the 8-bit destina-
tion field, and can be sent by software using a single write to the low doubleword of the ICR.
Shorthands are defined for the following cases: software self interrupt, IPIs to all processors in
the system including the sender, IPIs to all processors in the system excluding the sender.
00: (No Shorthand)
The destination is specified in the destination field.
01: (Self)
The issuing APIC is the one and only destination of the IPI. This destination
shorthand allows software to interrupt the processor on which it is execut-
ing. An APIC implementation is free to deliver the self-interrupt message
internally or to issue the message to the bus and “snoop” it as with any
other IPI message.
10: (All Including Self)
The IPI is sent to all processors in the system including the processor send-
ing the IPI. The APIC will broadcast an IPI message with the destination
field set to FH for Pentium and P6 family processors and to FFH for Pentium
4 and Intel Xeon processors.
11: (All Excluding Self)
The IPI is sent to all processors in a system with the exception of the pro-
cessor sending the IPI. The APIC broadcasts a message with the physical
destination mode and destination field set to FH for Pentium and P6 family
processors and to FFH for Pentium 4 and Intel Xeon processors. Support
for this destination shorthand in conjunction with the lowest-priority deliv-