35-308 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

187H

391

IA32_PERFEVTSEL1

Unique

See Table 35-2.

198H

408

IA32_PERF_STATUS

Shared

See Table 35-2.

199H

409

IA32_PERF_CTL

Unique

See Table 35-2.

19AH

410

IA32_CLOCK_

MODULATION

Unique

Clock Modulation (R/W) 
See Table 35-2.

19BH

411

IA32_THERM_

INTERRUPT

Unique

Thermal Interrupt Control (R/W) 
See Table 35-2.
See Section 14.7.2, “Thermal Monitor.”

19CH

412

IA32_THERM_STATUS

Unique

Thermal Monitor Status (R/W) 
See Table 35-2. 
See Section 14.7.2, “Thermal Monitor”.

19DH

413

MSR_THERM2_CTL

Unique

15:0

Reserved.

16

TM_SELECT (R/W) 
Mode of automatic thermal monitor:
0 =  Thermal Monitor 1 (thermally-initiated on-die modulation of 

the stop-clock duty cycle)

1 =  Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT 

has no effect. Neither TM1 nor TM2 will be enabled.

63:16

Reserved.

1A0H

416

IA32_MISC_ENABLE

Enable Miscellaneous Processor Features
(R/W) 
Allows a variety of processor functions to be enabled and disabled.

2:0

Reserved.

3

Unique

Automatic Thermal Control Circuit Enable (R/W) 
See Table 35-2. 

6:4

Reserved.

7

Shared

Performance Monitoring Available (R)
See Table 35-2.

9:8

Reserved.

10

Shared

FERR# Multiplexing Enable (R/W)
1 =  FERR# asserted by the processor to indicate a pending break 

event within the processor 

0 =  Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.

11

Shared

Branch Trace Storage Unavailable (RO)
See Table 35-2.

12

Reserved.

Table 35-44.  MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV 

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec