Vol. 3C 35-117

MODEL-SPECIFIC REGISTERS (MSRS)

33

Enable Load Latency on IA32_PMC1. (R/W)

34

Enable Load Latency on IA32_PMC2. (R/W)

35

Enable Load Latency on IA32_PMC3. (R/W)

63:36

Reserved.

3F6H

1014

MSR_PEBS_LD_LAT

Thread

See Section 18.7.1.2, “Load Latency Performance Monitoring 

Facility.”

15:0

Minimum threshold latency value of tagged load operation that will 

be counted. (R/W)

63:36

Reserved.

3F8H

1016

MSR_PKG_C3_RESIDENCY

Package

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

Package C3 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C3 

states. Count at the same frequency as the TSC.

3F9H

1017

MSR_PKG_C6_RESIDENCY

Package

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6 

states. Count at the same frequency as the TSC.

3FAH

1018

MSR_PKG_C7_RESIDENCY

Package

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

Package C7 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C7 

states. Count at the same frequency as the TSC.

3FCH

1020

MSR_CORE_C3_RESIDENCY Core

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

CORE C3 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C3 

states. Count at the same frequency as the TSC.

3FDH

1021

MSR_CORE_C6_RESIDENCY Core

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

CORE C6 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C6 

states. Count at the same frequency as the TSC.

400H

1024

IA32_MC0_CTL

Package

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

401H

1025

IA32_MC0_STATUS

Package

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

Table 35-13.  MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec