Vol. 3C 35-95

MODEL-SPECIFIC REGISTERS (MSRS)

N-1:0

LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its blocked state to service 

an SMI. The corresponding bit will be set if the logical processor is 

in one of the following states: Wait For SIPI or SENTER Sleep. 
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH, 

ECX=PKG_LVL):EBX[15:0] can be updated.

63:N

Reserved

500H

1280

IA32_SGX_SVN_STATUS

Core

Status and SVN Threshold of SGX Support for ACM (RO).

0

Lock. See Section 42.11.3, “Interactions with Authenticated Code 

Modules (ACMs)”

15:1

Reserved.

23:16

SGX_SVN_SINIT. See Section 42.11.3, “Interactions with 

Authenticated Code Modules (ACMs)”

63:24

Reserved.

560H

1376

IA32_RTIT_OUTPUT_BASE

Core

Trace Output Base Register (R/W). See Table 35-2. 

561H

1377

IA32_RTIT_OUTPUT_MASK

_PTRS

Core

Trace Output Mask Pointers Register (R/W). See Table 35-2. 

570H

1392

IA32_RTIT_CTL

Core

Trace Control Register (R/W)

0

TraceEn

1

CYCEn

2

OS

3

User

6:4

Reserved, MBZ

7

CR3 filter

8

ToPA; writing 0 will #GP if also setting TraceEn

9

MTCEn

10

TSCEn

11

DisRETC

12

Reserved, MBZ

13

BranchEn

17:14

MTCFreq

18

Reserved, MBZ

22:19

CYCThresh

23

Reserved, MBZ

27:24

PSBFreq

31:28

Reserved, MBZ

35:32

ADDR0_CFG

39:36

ADDR1_CFG

63:40

Reserved, MBZ.

Table 35-12.   MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)

Address

Register Name

Scope

Bit Description

 Hex

Dec