4-26 Vol. 3A
PAGING
11:9
Ignored
12 (PAT)
Indirectly determines the memory type used to access the 2-MByte page referenced by this entry (see Section
20:13
Reserved (must be 0)
(M–1):21
Physical address of the 2-MByte page referenced by this entry
51:M
Reserved (must be 0)
58:52
Ignored
62:59
Protection key; if CR4.PKE = 1, determines the protection key of the page (see Section 4.6.2); ignored otherwise
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte page controlled by
this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-18. Format of an IA-32e Page-Directory Entry that References a Page Table
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte region controlled by this entry (see Section
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page table referenced by this
entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 4-17)
11:8
Ignored
(M–1):12
Physical address of 4-KByte aligned page table referenced by this entry
51:M
Reserved (must be 0)
62:52
Ignored
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte region controlled
by this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-17. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page (Contd.)
Bit
Position(s)
Contents