FXSAVE—Save x87 FPU, MMX Technology, and SSE State

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-413

The destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte 
boundary. A misaligned destination operand will result in a general-protection (#GP) exception being generated (or 
in some cases, an alignment check exception [#AC]).
The FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception 
handler needs to save and examine the current state of the x87 FPU, MMX technology, and/or XMM and MXCSR 
registers.
The fields in Table 3-43 are defined in Table 3-44.

Reserved

304

Reserved

320

Reserved

336

Reserved

352

Reserved

368

Reserved

384

Reserved

400

Reserved

416

Reserved

432

Reserved

448

Available

464

Available

480

Available

496

Table 3-44.  Field Definitions 

Field

Definition

FCW

x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel® 64 and IA-32 Architectures Software 

Developer’s Manual, Volume 1, for the layout of the x87 FPU control word.

FSW

x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel® 64 and IA-32 Architectures Software 

Developer’s Manual, Volume 1, for the layout of the x87 FPU status word.

Abridged FTW

x87 FPU Tag Word (8 bits). The tag information saved here is abridged, as described in the following 

paragraphs.

FOP

x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved. 

See Figure 8-8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for 

the layout of the x87 FPU opcode field.

FIP

x87 FPU Instruction Pointer Offset (64 bits). The contents of this field differ depending on the current 

addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the FXSAVE instruction was 

executed:
32-bit mode — 32-bit IP offset.
16-bit mode — low 16 bits are IP offset; high 16 bits are reserved.
64-bit mode with REX.W — 64-bit IP offset.
64-bit mode without REX.W — 32-bit IP offset.
See “x87 FPU Instruction and Operand (Data) Pointers” in Chapter 8 of the Intel® 64 and IA-32 

Architectures Software Developer’s Manual, Volume 1, for a description of the x87 FPU instruction 

pointer.

Table 3-43.  Non-64-bit-Mode Layout of FXSAVE and FXRSTOR 

Memory Region (Contd.)

15

14

13  12

11 10

9

 8

7

6

5 

4

3

2

1

0