FXSAVE—Save x87 FPU, MMX Technology, and SSE State

INSTRUCTION SET REFERENCE, A-L

3-412 Vol. 2A

FXSAVE—Save x87 FPU, MMX Technology, and SSE State

Instruction Operand Encoding

Description

Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory loca-
tion specified in the destination operand. The content layout of the 512 byte region depends on whether the 
processor is operating in non-64-bit operating modes or 64-bit sub-mode of IA-32e mode. 
Bytes 464:511 are available to software use. The processor does not write to bytes 464:511 of an FXSAVE area. 
The operation of FXSAVE in non-64-bit modes is described first.

Non-64-Bit Mode Operation

Table 3-43 shows the layout of the state information in memory when the processor is operating in legacy modes.

Opcode/

Instruction

Op/ 

En

64-Bit 

Mode

Compat/

Leg Mode

Description

0F AE /0
FXSAVE m512byte

M

Valid

Valid

Save the x87 FPU, MMX, XMM, and MXCSR 

register state to m512byte.

REX.W+ 0F AE /0
FXSAVE64 m512byte

M

Valid

N.E.

Save the x87 FPU, MMX, XMM, and MXCSR 

register state to m512byte.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

NA

NA

NA

Table 3-43.  Non-64-bit-Mode Layout of FXSAVE and FXRSTOR 

Memory Region

15

14

13  12

11 10

9

 8

7

6

5 

4

3

2

1

0

Rsvd

FCS

FIP[31:0]

FOP

Rsvd

FTW

FSW

FCW

0

MXCSR_MASK

MXCSR

Rsrvd

FDS

FDP[31:0]

16

Reserved

ST0/MM0

32

Reserved

ST1/MM1

48

Reserved

ST2/MM2

64

Reserved

ST3/MM3

80

Reserved

ST4/MM4

96

Reserved

ST5/MM5

112

Reserved

ST6/MM6

128

Reserved

ST7/MM7

144

XMM0

160

XMM1

176

XMM2

192

XMM3

208

XMM4

224

XMM5

240

XMM6

256

XMM7

272

Reserved

288