Vol. 1 13-11

MANAGING STATE USING THE XSAVE FEATURE SET

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BNDCSR state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=4):EBX enumerates the offset of the section of the extended 
region of the XSAVE area used for BNDCSR state (when the standard format of the extended region is used). 
CPUID.(EAX=0DH,ECX=6):EAX enumerates the size (in bytes) required for BNDCSR state. In the BNDSCR 
section, bytes 7:0 are used for BNDCFGU and bytes 15:8 are used for BNDSTATUS.

Both components of MPX state are XSAVE-managed and the MPX feature is XSAVE-enabled. The XSAVE feature set 
can operate on MPX state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to 
manage MPX state (XCR0[4:3] = 11b). MPX instructions cannot be used unless the XSAVE feature set is enabled 
and has been configured to manage MPX state.

13.5.5 AVX-512 

State

The register state used by the Intel

®

 Advanced Vector Extensions 512 (AVX-512) comprises the MXCSR register, 

the 8 64-bit opmask registers k0–k7, and 32 512-bit vector registers called ZMM0–ZMM31. For each i, 0 <= i <= 
15, the low 256 bits of register ZMMi is identical to the AVX register YMMi. Thus, the new state register state added 
by AVX comprises the following user state components:

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The opmask registers, collectively called opmask state.

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The upper 256 bits of the registers ZMM0–ZMM15. These 16 256-bit values are denoted ZMM0_H–ZMM15_H 
and are collectively called ZMM_Hi256 state.

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The 16 512-bit registers ZMM16–ZMM31, collectively called Hi16_ZMM state.

Together, these three state components compose AVX-512 state.
As noted in Section 13.1, the XSAVE feature set manages AVX-512 state as state components 5–7. Thus, AVX-512 
state is located in the extended region of the XSAVE area (see Section 13.4.3). The following items detail how 
these state components are organized in this region:

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Opmask state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=5):EBX enumerates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of the XSAVE area used for opmask state (when the standard 
format of the extended region is used). CPUID.(EAX=0DH,ECX=5):EAX enumerates the size (in bytes) 
required for opmask state. The opmask section is used for the 8 64-bit bound registers k0–k7, with 
bytes 8i+7:8i being used for ki.

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ZMM_Hi256 state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=6):EBX enumerates the offset of the section of the extended 
region of the XSAVE area used for ZMM_Hi256 state (when the standard format of the extended region is 
used). CPUID.(EAX=0DH,ECX=6):EAX enumerates the size (in bytes) required for ZMM_Hi256 state.
The XSAVE feature set partitions ZMM0_H–ZMM15_H in a manner similar to that used for the XMM registers 
(see Section 13.5.2). Bytes 255:0 of the ZMM_Hi256-state section are used for ZMM0_H–ZMM7_H. 
Bytes 511:256 are used for ZMM8_H–ZMM15_H, but they are used only in 64-bit mode. Executions of XSAVE, 
XSAVEOPT, XSAVEC, and XSAVES outside 64-bit mode do not modify bytes 511:256; executions of XRSTOR 
and XRSTORS outside 64-bit mode do not update ZMM8_H–ZMM15_H. See Section 13.13. In general, 
bytes 32i+31:32i are used for ZMMi_H (for 0 ≤ i ≤ 15).

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Hi16_ZMM state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=7):EBX enumerates the offset of the section of the extended 
region of the XSAVE area used for Hi16_ZMM state (when the standard format of the extended region is used). 
CPUID.(EAX=0DH,ECX=7):EAX enumerates the size (in bytes) required for Hi16_ZMM state.
The XSAVE feature set accesses Hi16_ZMM state only in 64-bit mode. Executions of XSAVE, XSAVEOPT, 
XSAVEC, and XSAVES outside 64-bit mode do not modify the Hi16_ZMM section; executions of XRSTOR and 
XRSTORS outside 64-bit mode do not update ZMM16–ZMM31. See Section 13.13. In general, 
bytes 64(i-16)+63:64(i-16) are used for ZMMi (for 16 ≤ i ≤ 31).

All three components of AVX-512 state are XSAVE-managed and the AVX-512 feature is XSAVE-enabled. The 
XSAVE feature set can operate on AVX-512 state only if the feature set is enabled (CR4.OSXSAVE = 1) and has 
been configured to manage AVX-512 state (XCR0[7:5] = 111b). AVX-512 instructions cannot be used unless the 
XSAVE feature set is enabled and has been configured to manage AVX-512 state.