Vol. 1 8-1

CHAPTER 8

PROGRAMMING WITH THE X87 FPU

The x87 Floating-Point Unit (FPU) provides high-performance floating-point processing capabilities for use in 
graphics processing, scientific, engineering, and business applications. It supports the floating-point, integer, and 
packed BCD integer data types and the floating-point processing algorithms and exception handling architecture 
defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic.
This chapter describes the x87 FPU’s execution environment and instruction set. It also provides exception 
handling information that is specific to the x87 FPU. Refer to the following chapters or sections of chapters for addi-
tional information about x87 FPU instructions and floating-point operations:

•

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, provide detailed descrip-
tions of x87 FPU instructions.

•

Section 4.2.2, “Floating-Point Data Types,” Section 4.2.1.2, “Signed Integers,” and Section 4.7, “BCD and 
Packed BCD Integers,” describe the floating-point, integer, and BCD data types.

•

Section 4.9, “Overview of Floating-Point Exceptions,” Section 4.9.1, “Floating-Point Exception Conditions,” and 
Section 4.9.2, “Floating-Point Exception Priority,” give an overview of the floating-point exceptions that the x87 
FPU can detect and report.

8.1 

X87 FPU EXECUTION ENVIRONMENT

The x87 FPU represents a separate execution environment within the IA-32 architecture (see Figure 8-1). This 
execution environment consists of eight data registers (called the x87 FPU data registers) and the following 
special-purpose registers: 

•

Status register

•

Control register

•

Tag word register

•

Last instruction pointer register

•

Last data (operand) pointer register

•

Opcode register

These registers are described in the following sections.
The x87 FPU executes instructions from the processor’s normal instruction stream. The state of the x87 FPU is inde-
pendent from the state of the basic execution environment and from the state of SSE/SSE2/SSE3 extensions. 
However, the x87 FPU and Intel MMX technology share state because the MMX registers are aliased to the x87 FPU 
data registers. Therefore, when writing code that uses x87 FPU and MMX instructions, the programmer must 
explicitly manage the x87 FPU and MMX state (see Section 9.5, “Compatibility with x87 FPU Architecture”).

8.1.1 

x87 FPU in 64-Bit Mode and Compatibility Mode

In compatibility mode and 64-bit mode, x87 FPU instructions function like they do in protected mode. Memory 
operands are specified using the ModR/M, SIB encoding that is described in Section 3.7.5, “Specifying an Offset.”

8.1.2 

x87 FPU Data Registers

The x87 FPU data registers (shown in Figure 8-1) consist of eight 80-bit registers. Values are stored in these regis-
ters in the double extended-precision floating-point format shown in Figure 4-3. When floating-point, integer, or 
packed BCD integer values are loaded from memory into any of the x87 FPU data registers, the values are auto-
matically converted into double extended-precision floating-point format (if they are not already in that format). 
When computation results are subsequently transferred back into memory from any of the x87 FPU registers, the