9-8 Vol. 1

PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY

9.4.7 Shift 

Instructions

The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified 
number of bit positions.
The PSLLW/PSLLD/PSLLQ (shift packed data left logical) instructions and the PSRLW/PSRLD/PSRLQ (shift packed 
data right logical) instructions perform a logical left or right shift of the data elements and fill the empty high or low 
order bit positions with zeros. These instructions operate on packed words, doublewords, and quadwords.
The PSRAW/PSRAD (shift packed data right arithmetic) instructions perform an arithmetic right shift, copying the 
sign bit for each data element into empty bit positions on the upper end of each data element. This instruction 
operates on packed words and doublewords. 

9.4.8 EMMS 

Instruction

The EMMS instruction empties the MMX state by setting the tags in x87 FPU tag word to 11B, indicating empty 
registers. This instruction must be executed at the end of an MMX routine before calling other routines that can 
execute floating-point instructions. See Section 9.6.3, “Using the EMMS Instruction,” for more information on the 
use of this instruction.

9.5 

COMPATIBILITY WITH X87 FPU ARCHITECTURE

The MMX state is aliased to the x87 FPU state. No new states or modes have been added to IA-32 architecture to 
support the MMX technology. The same floating-point instructions that save and restore the x87 FPU state also 
handle the MMX state (for example, during context switching).
MMX technology uses the same interface techniques between the x87 FPU and the operating system (primarily for 
task switching purposes). For more details, see Chapter 12, “Intel® MMX™ Technology System Programming,” in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

9.5.1 

MMX Instructions and the x87 FPU Tag Word

After each MMX instruction, the entire x87 FPU tag word is set to valid (00B). The EMMS instruction (empty MMX 
state) sets the entire x87 FPU tag word to empty (11B). 
Chapter 12, “Intel® MMX™ Technology System Programming,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A, provides additional information about the effects of x87 FPU and MMX instructions 
on the x87 FPU tag word. For a description of the tag word, see Section 8.1.7, “x87 FPU Tag Word.”

9.6 

WRITING APPLICATIONS WITH MMX CODE

The following sections give guidelines for writing application code that uses MMX technology.

9.6.1 

Checking for MMX Technology Support

Before an application attempts to use the MMX technology, it should check that it is present on the processor. Check 
by following these steps:
1. Check that the processor supports the CPUID instruction by attempting to execute the CPUID instruction. If the 

processor does not support the CPUID instruction, this will generate an invalid-opcode exception (#UD).

2. Check that the processor supports the MMX technology 

(if CPUID.01H:EDX.MMX[bit 23] = 1).

3. Check that emulation of the x87 FPU is disabled (if CR0.EM[bit 2] = 0).
If the processor attempts to execute an unsupported MMX instruction or attempts to execute an MMX instruction 
with CR0.EM[bit 2] set, this generates an invalid-opcode exception (#UD).