19-128 Vol. 3B
PERFORMANCE-MONITORING EVENTS
63
H
See
and
BUS_LOCK_
CLOCKS.(Core and Bus
Agents)
Bus cycles when a
LOCK signal asserted.
This event counts the number of bus cycles, during which
the LOCK signal is asserted on the bus. A LOCK signal is
asserted when there is a locked memory access, due to:
• Uncacheable memory.
• Locked operation that spans two cache lines.
• Page-walk from an uncacheable page table.
Bus locks have a very high performance penalty and it is
highly recommended to avoid such accesses.
64
H
See
BUS_DATA_
RCV.(Core)
Bus cycles while
processor receives
data.
This event counts the number of bus cycles during which
the processor is busy receiving data.
65
H
See
and
BUS_TRANS_BRD.(Core
and Bus Agents)
Burst read bus
transactions.
This event counts the number of burst read transactions
including:
• L1 data cache read misses (and L1 data cache hardware
prefetches).
• L2 hardware prefetches by the DPL and L2 streamer.
• IFU read misses of cacheable lines.
It does not include RFO transactions.
66H
See
and
BUS_TRANS_RFO.(Core
and Bus Agents)
RFO bus transactions. This event counts the number of Read For Ownership (RFO)
bus transactions, due to store operations that miss the L1
data cache and the L2 cache. It also counts RFO bus
transactions due to locked operations.
67H
See
and
BUS_TRANS_WB.
(Core and Bus Agents)
Explicit writeback bus
transactions.
This event counts all explicit writeback bus transactions due
to dirty line evictions. It does not count implicit writebacks
due to invalidation by a snoop request.
68H
See
and
BUS_TRANS_
IFETCH.(Core and Bus
Agents)
Instruction-fetch bus
transactions.
This event counts all instruction fetch full cache line bus
transactions.
69
H
See
and
BUS_TRANS_
INVAL.(Core and Bus
Agents)
Invalidate bus
transactions.
This event counts all invalidate transactions. Invalidate
transactions are generated when:
• A store operation hits a shared line in the L2 cache.
• A full cache line write misses the L2 cache or hits a
shared line in the L2 cache.
6AH
See
and
BUS_TRANS_
PWR.(Core and Bus Agents)
Partial write bus
transaction.
This event counts partial write bus transactions.
Table 19-23. Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Event
Num
Umask
Value
Event Name
Definition
Description and
Comment