Vol. 3B 19-45

PERFORMANCE-MONITORING EVENTS

28H

01H

L2_L1D_WB_RQSTS.MISS

Not rejected writebacks from L1D to L2 cache lines 

that missed L2.

28H

02H

L2_L1D_WB_RQSTS.HIT_S

Not rejected writebacks from L1D to L2 cache lines 

in S state.

28H

04H

L2_L1D_WB_RQSTS.HIT_E

Not rejected writebacks from L1D to L2 cache lines 

in E state.

28H

08H

L2_L1D_WB_RQSTS.HIT_M

Not rejected writebacks from L1D to L2 cache lines 

in M state.

28H

0FH

L2_L1D_WB_RQSTS.ALL

Not rejected writebacks from L1D to L2 cache.

2EH

4FH

LONGEST_LAT_CACHE.REFERE

NCE

This event counts requests originating from the 

core that reference a cache line in the last level 

cache. 

See Table 19-1.

2EH

41H

LONGEST_LAT_CACHE.MISS

This event counts each cache miss condition for 

references to the last level cache. 

See Table 19-1.

3CH

00H

CPU_CLK_UNHALTED.THREAD

_P

Counts the number of thread cycles while the 

thread is not in a halt state. The thread enters the 

halt state when it is running the HLT instruction. 

The core frequency may change from time to time 

due to power or thermal throttling. 

See Table 19-1.

3CH

01H

CPU_CLK_THREAD_UNHALTED

.REF_XCLK

Increments at the frequency of XCLK (100 MHz) 

when not halted.

See Table 19-1.

48H

01H

L1D_PEND_MISS.PENDING

Increments the number of outstanding L1D misses 

every cycle. Set Cmask = 1 and Edge =1 to count 

occurrences.

PMC2 only;
Set Cmask = 1 to count 

cycles. 

49H

01H

DTLB_STORE_MISSES.MISS_CA

USES_A_WALK

Miss in all TLB levels causes a page walk of any page 

size (4K/2M/4M/1G).

49H

02H

DTLB_STORE_MISSES.WALK_C

OMPLETED

Miss in all TLB levels causes a page walk that 

completes of any page size (4K/2M/4M/1G).

49H

04H

DTLB_STORE_MISSES.WALK_D

URATION

Cycles PMH is busy with this walk.

49H

10H

DTLB_STORE_MISSES.STLB_HI

T

Store operations that miss the first TLB level but hit 

the second and do not cause page walks.

4CH

01H

LOAD_HIT_PRE.SW_PF

Not SW-prefetch load dispatches that hit fill buffer 

allocated for S/W prefetch.

4CH

02H

LOAD_HIT_PRE.HW_PF

Not SW-prefetch load dispatches that hit fill buffer 

allocated for H/W prefetch.

4EH

02H

HW_PRE_REQ.DL1_MISS

Hardware Prefetch requests that miss the L1D 

cache. A request is being counted each time it 

access the cache & miss it, including if a block is 

applicable or if hit the Fill Buffer for example.

This accounts for both L1 

streamer and IP-based 

(IPP) HW prefetchers. 

51H

01H

L1D.REPLACEMENT

Counts the number of lines brought into the L1 data 

cache.

51H

02H

L1D.ALLOCATED_IN_M

Counts the number of allocations of modified L1D 

cache lines. 

51H

04H

L1D.EVICTION

Counts the number of modified lines evicted from 

the L1 data cache due to replacement. 

Table 19-13.  Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™ 

i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family 

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment