Vol. 3B 19-39
PERFORMANCE-MONITORING EVENTS
A3H
02H
CYCLE_ACTIVITY.CYCLES_LDM_P
ENDING
Cycles with pending memory loads. Set AnyThread
to count per core.
Restricted to counters 0-
3 when HTT is disabled.
A3H
04H
CYCLE_ACTIVITY.CYCLES_NO_EX
ECUTE
Cycles of dispatch stalls. Set AnyThread to count
per core.
Restricted to counters 0-
3 when HTT is disabled.
A3H
05H
CYCLE_ACTIVITY.STALLS_L2_PEN
DING
Number of loads missed L2.
Restricted to counters 0-
3 when HTT is disabled.
A3H
06H
CYCLE_ACTIVITY.STALLS_LDM_P
ENDING
Restricted to counters 0-
3 when HTT is disabled.
A3H
08H
CYCLE_ACTIVITY.CYCLES_L1D_PE
NDING
Cycles with pending L1 cache miss loads. Set
AnyThread to count per core.
PMC2 only.
A3H
0CH
CYCLE_ACTIVITY.STALLS_L1D_PE
NDING
Execution stalls due to L1 data cache miss loads.
Set Cmask=0CH.
PMC2 only.
A8H
01H
LSD.UOPS
Number of Uops delivered by the LSD.
ABH
01H
DSB2MITE_SWITCHES.COUNT
Number of DSB to MITE switches.
ABH
02H
DSB2MITE_SWITCHES.PENALTY_
CYCLES
Cycles DSB to MITE switches caused delay.
ACH
08H
DSB_FILL.EXCEED_DSB_LINES
DSB Fill encountered > 3 DSB lines.
AEH
01H
ITLB.ITLB_FLUSH
Counts the number of ITLB flushes, includes
4k/2M/4M pages.
B0H
01H
OFFCORE_REQUESTS.DEMAND_D
ATA_RD
Demand data read requests sent to uncore.
B0H
02H
OFFCORE_REQUESTS.DEMAND_C
ODE_RD
Demand code read requests sent to uncore.
B0H
04H
OFFCORE_REQUESTS.DEMAND_R
FO
Demand RFO read requests sent to uncore,
including regular RFOs, locks, ItoM.
B0H
08H
OFFCORE_REQUESTS.ALL_DATA_
RD
Data read requests sent to uncore (demand and
prefetch).
B1H
01H
UOPS_EXECUTED.THREAD
Counts total number of uops to be executed per-
thread each cycle. Set Cmask = 1, INV =1 to count
stall cycles.
B1H
02H
UOPS_EXECUTED.CORE
Counts total number of uops to be executed per-
core each cycle.
Do not need to set ANY.
B7H
01H
OFFCORE_RESPONSE_0
See Section 18.9.5, “Off-core Response
Requires MSR 01A6H.
BBH
01H
OFFCORE_RESPONSE_1
See Section 18.9.5, “Off-core Response
Requires MSR 01A7H.
BDH
01H
TLB_FLUSH.DTLB_THREAD
DTLB flush attempts of the thread-specific entries.
BDH
20H
TLB_FLUSH.STLB_ANY
Count number of STLB flush attempts.
C0H
00H
INST_RETIRED.ANY_P
Number of instructions at retirement.
See Table 19-1.
C0H
01H
INST_RETIRED.PREC_DIST
Precise instruction retired event with HW to reduce
effect of PEBS shadow in IP distribution.
PMC1 only.
C1H
08H
OTHER_ASSISTS.AVX_STORE
Number of assists associated with 256-bit AVX
store operations.
C1H
10H
OTHER_ASSISTS.AVX_TO_SSE
Number of transitions from AVX-256 to legacy SSE
when penalty applicable.
Table 19-11. Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment