Vol. 3B 19-35
PERFORMANCE-MONITORING EVENTS
24H
01H
L2_RQSTS.DEMAND_DATA_RD_H
IT
Demand Data Read requests that hit L2 cache.
24H
03H
L2_RQSTS.ALL_DEMAND_DATA_
RD
Counts any demand and L1 HW prefetch data load
requests to L2.
24H
04H
L2_RQSTS.RFO_HITS
Counts the number of store RFO requests that hit
the L2 cache.
24H
08H
L2_RQSTS.RFO_MISS
Counts the number of store RFO requests that miss
the L2 cache.
24H
0CH
L2_RQSTS.ALL_RFO
Counts all L2 store RFO requests.
24H
10H
L2_RQSTS.CODE_RD_HIT
Number of instruction fetches that hit the L2 cache.
24H
20H
L2_RQSTS.CODE_RD_MISS
Number of instruction fetches that missed the L2
cache.
24H
30H
L2_RQSTS.ALL_CODE_RD
Counts all L2 code requests.
24H
40H
L2_RQSTS.PF_HIT
Counts all L2 HW prefetcher requests that hit L2.
24H
80H
L2_RQSTS.PF_MISS
Counts all L2 HW prefetcher requests that missed
L2.
24H
C0H
L2_RQSTS.ALL_PF
Counts all L2 HW prefetcher requests.
27H
01H
L2_STORE_LOCK_RQSTS.MISS
RFOs that miss cache lines.
27H
08H
L2_STORE_LOCK_RQSTS.HIT_M
RFOs that hit cache lines in M state.
27H
0FH
L2_STORE_LOCK_RQSTS.ALL
RFOs that access cache lines in any state.
28H
01H
L2_L1D_WB_RQSTS.MISS
Not rejected writebacks that missed LLC.
28H
04H
L2_L1D_WB_RQSTS.HIT_E
Not rejected writebacks from L1D to L2 cache lines
in E state.
28H
08H
L2_L1D_WB_RQSTS.HIT_M
Not rejected writebacks from L1D to L2 cache lines
in M state.
28H
0FH
L2_L1D_WB_RQSTS.ALL
Not rejected writebacks from L1D to L2 cache lines
in any state.
2EH
4FH
LONGEST_LAT_CACHE.REFERENC
E
This event counts requests originating from the
core that reference a cache line in the last level
cache.
2EH
41H
LONGEST_LAT_CACHE.MISS
This event counts each cache miss condition for
references to the last level cache.
3CH
00H
CPU_CLK_UNHALTED.THREAD_P Counts the number of thread cycles while the
thread is not in a halt state. The thread enters the
halt state when it is running the HLT instruction.
The core frequency may change from time to time
due to power or thermal throttling.
See Table 19-1.
3CH
01H
CPU_CLK_THREAD_UNHALTED.R
EF_XCLK
Increments at the frequency of XCLK (100 MHz)
when not halted.
See Table 19-1.
48H
01H
L1D_PEND_MISS.PENDING
Increments the number of outstanding L1D misses
every cycle. Set Cmask = 1 and Edge =1 to count
occurrences.
PMC2 only;
Set Cmask = 1 to count
cycles.
49H
01H
DTLB_STORE_MISSES.MISS_CAUS
ES_A_WALK
Miss in all TLB levels causes a page walk of any
page size (4K/2M/4M/1G).
Table 19-11. Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors (Contd.)
Event
Num.
Umask
Value
Event Mask Mnemonic
Description
Comment