19-28 Vol. 3B

PERFORMANCE-MONITORING EVENTS

C4H

08H

BR_INST_RETIRED.NEAR_RETU

RN

Counts the number of near return instructions 

retired.

Supports PEBS.

C4H

10H

BR_INST_RETIRED.NOT_TAKEN Counts the number of not taken branch instructions 

retired. 

C4H

20H

BR_INST_RETIRED.NEAR_TAKE

N

Number of near taken branches retired.

Supports PEBS.

C4H

40H

BR_INST_RETIRED.FAR_BRANC

H

Number of far branches retired.

C5H

00H

BR_MISP_RETIRED.ALL_BRANC

HES

Mispredicted branch instructions at retirement.

See Table 19-1.

C5H

01H

BR_MISP_RETIRED.CONDITIONA

L

Mispredicted conditional branch instructions retired.  Supports PEBS.

C5H

04H

BR_MISP_RETIRED.ALL_BRANC

HES

Mispredicted macro branch instructions retired.

Supports PEBS.

C5H

20H

BR_MISP_RETIRED.NEAR_TAKE

N

Number of near branch instructions retired that 

were taken but mispredicted.

CAH

02H

FP_ASSIST.X87_OUTPUT

Number of X87 FP assists due to output values.

CAH

04H

FP_ASSIST.X87_INPUT

Number of X87 FP assists due to input values.

CAH

08H

FP_ASSIST.SIMD_OUTPUT

Number of SIMD FP assists due to output values.

CAH

10H

FP_ASSIST.SIMD_INPUT

Number of SIMD FP assists due to input values.

CAH

1EH

FP_ASSIST.ANY

Cycles with any input/output SSE* or FP assists.

CCH

20H

ROB_MISC_EVENTS.LBR_INSER

TS

Count cases of saving new LBR records by hardware. 

CDH

01H

MEM_TRANS_RETIRED.LOAD_L

ATENCY

Randomly sampled loads whose latency is above a 

user defined threshold. A small fraction of the overall 

loads are sampled due to randomization.

Specify threshold in MSR 

3F6H.

D0H

11H

MEM_UOPS_RETIRED.STLB_MIS

S_LOADS

Retired load uops that miss the STLB.

Supports PEBS and 

DataLA.

D0H

12H

MEM_UOPS_RETIRED.STLB_MIS

S_STORES

Retired store uops that miss the STLB.

Supports PEBS and 

DataLA.

D0H

21H

MEM_UOPS_RETIRED.LOCK_LOA

DS

Retired load uops with locked access.

Supports PEBS and 

DataLA.

D0H

41H

MEM_UOPS_RETIRED.SPLIT_LO

ADS

Retired load uops that split across a cacheline 

boundary.

Supports PEBS and 

DataLA.

D0H

42H

MEM_UOPS_RETIRED.SPLIT_ST

ORES

Retired store uops that split across a cacheline 

boundary.

Supports PEBS and 

DataLA.

D0H

81H

MEM_UOPS_RETIRED.ALL_LOAD

S

All retired load uops.

Supports PEBS and 

DataLA.

D0H

82H

MEM_UOPS_RETIRED.ALL_STOR

ES

All retired store uops.

Supports PEBS and 

DataLA.

D1H

01H

MEM_LOAD_UOPS_RETIRED.L1_

HIT

Retired load uops with L1 cache hits as data sources. Supports PEBS and 

DataLA.

D1H

02H

MEM_LOAD_UOPS_RETIRED.L2_

HIT

Retired load uops with L2 cache hits as data sources. Supports PEBS and 

DataLA.

Table 19-7.  Non-Architectural Performance Events in the Processor Core of 

4th Generation Intel® Core™ Processors (Contd.)

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment