Vol. 3B 19-23

PERFORMANCE-MONITORING EVENTS

3CH

00H

CPU_CLK_UNHALTED.THREAD_

P

Counts the number of thread cycles while the thread 

is not in a halt state. The thread enters the halt state 

when it is running the HLT instruction. The core 

frequency may change from time to time due to 

power or thermal throttling. 

See Table 19-1.

3CH

01H

CPU_CLK_THREAD_UNHALTED.

REF_XCLK

Increments at the frequency of XCLK (100 MHz) 

when not halted.

See Table 19-1.

48H

01H

L1D_PEND_MISS.PENDING

Increments the number of outstanding L1D misses 

every cycle. Set Cmask = 1 and Edge =1 to count 

occurrences.

Counter 2 only.
Set Cmask = 1 to count 

cycles. 

49H

01H

DTLB_STORE_MISSES.MISS_CAU

SES_A_WALK

Miss in all TLB levels causes a page walk of any page 

size (4K/2M/4M/1G).

49H

02H

DTLB_STORE_MISSES.WALK_CO

MPLETED_4K

Completed page walks due to store misses in one or 

more TLB levels of 4K page structure.

49H

04H

DTLB_STORE_MISSES.WALK_CO

MPLETED_2M_4M

Completed page walks due to store misses in one or 

more TLB levels of 2M/4M page structure.

49H

0EH

DTLB_STORE_MISSES.WALK_CO

MPLETED

Completed page walks due to store miss in any TLB 

levels of any page size (4K/2M/4M/1G).

49H

10H

DTLB_STORE_MISSES.WALK_DU

RATION

Cycles PMH is busy with this walk.

49H

20H

DTLB_STORE_MISSES.STLB_HIT

_4K

Store misses that missed DTLB but hit STLB (4K).

49H

40H

DTLB_STORE_MISSES.STLB_HIT

_2M

Store misses that missed DTLB but hit STLB (2M).

49H

60H

DTLB_STORE_MISSES.STLB_HIT Store operations that miss the first TLB level but hit 

the second and do not cause page walks.

49H

80H

DTLB_STORE_MISSES.PDE_CAC

HE_MISS

DTLB store misses with low part of linear-to-physical 

address translation missed.

4CH

01H

LOAD_HIT_PRE.SW_PF

Non-SW-prefetch load dispatches that hit fill buffer 

allocated for S/W prefetch.

4CH

02H

LOAD_HIT_PRE.HW_PF

Non-SW-prefetch load dispatches that hit fill buffer 

allocated for H/W prefetch.

51H

01H

L1D.REPLACEMENT

Counts the number of lines brought into the L1 data 

cache.

58H

04H

MOVE_ELIMINATION.INT_NOT_E

LIMINATED

Number of integer move elimination candidate uops 

that were not eliminated.

58H

08H

MOVE_ELIMINATION.SIMD_NOT_

ELIMINATED

Number of SIMD move elimination candidate uops 

that were not eliminated.

58H

01H

MOVE_ELIMINATION.INT_ELIMIN

ATED

Number of integer move elimination candidate uops 

that were eliminated.

58H

02H

MOVE_ELIMINATION.SIMD_ELIMI

NATED

Number of SIMD move elimination candidate uops 

that were eliminated.

5CH

01H

CPL_CYCLES.RING0

Unhalted core cycles when the thread is in ring 0.

Use Edge to count 

transition.

5CH

02H

CPL_CYCLES.RING123

Unhalted core cycles when the thread is not in ring 0.

5EH

01H

RS_EVENTS.EMPTY_CYCLES

Cycles the RS is empty for the thread.

Table 19-7.  Non-Architectural Performance Events in the Processor Core of 

4th Generation Intel® Core™ Processors (Contd.)

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment