Vol. 3B 14-17

POWER AND THERMAL MANAGEMENT

cycles when the package is in C2 state and at least one processor core in this package was forced into idle state 
due to HDC. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault. Default = zero 
(0). 

A value of zero in MSR_PKG_HDC_SHALLOW_RESIDENCY indicates either HDC is not supported or this processor 
package never serviced any forced HDC idle. 

MSR_PKG_HDC_DEEP_RESIDENCY

The counter MSR_PKG_HDC_DEEP_RESIDENCY allows software to track HDC residency time when the package is 
in a software-specified package Cx state, all processor cores in the package are not active and at least one logical 
processor was forced into idle state due to HDC. Selection of a specific package Cx state can be configured using 
MSR_PKG_HDC_CONFIG. The layout of the MSR_PKG_HDC_DEEP_RESIDENCY is shown in Figure 14-17. There is 
one MSR_PKG_HDC_DEEP_RESIDENCY per package. The bit fields are described below: 

•

Pkg_Cx_Duty_Cycle_Cnt (bits 63:0, R/O) — Stores accumulated HDC forced-idle cycle count of this 
processor core since last RESET. This counter increments at the same rate of the TSC. The count is updated 
only after package C-state exit from a forced idle state. At each update, the increment counts cycles when the 
package is in the software-configured Cx state and at least one processor core in this package was forced into 
idle state due to HDC. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault. 
Default = zero (0). 

A value of zero in MSR_PKG_HDC_SHALLOW_RESIDENCY indicates either HDC is not supported or this processor 
package never serviced any forced HDC idle. 

MSR_PKG_HDC_CONFIG

MSR_PKG_HDC_CONFIG allows software to configure the package Cx state that the counter 
MSR_PKG_HDC_DEEP_RESIDENCY monitors. The layout of the MSR_PKG_HDC_CONFIG is shown in Figure 14-18. 
There is one MSR_PKG_HDC_CONFIG per package. The bit fields are described below: 

•

Pkg_Cx_Monitor (bits 2:0, R/W) — Selects which package C-state the MSR_HDC_DEEP_RESIDENCY 
counter will monitor. The encoding of the HDC_Cx_Monitor field are: 0: no-counting; 1: count package C2 only, 
2: count package C3 and deeper; 3: count package C6 and deeper; 4: count package C7 and deeper; other 
encodings are reserved. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault. 
Default = zero (0). 

•

Bits 63:3 are reserved and must be zero.

Figure 14-17.  MSR_PKG_HDC_DEEP_RESIDENCY MSR

Figure 14-18.  MSR_PKG_HDC_CONFIG MSR

63

0

Pkg_Cx_duty_cycle_cnt

63

0

Reserved

2

HDC_Cx_Monitor

Reserved