9-4 Vol. 3A

PROCESSOR MANAGEMENT AND INITIALIZATION

IA32_PMCx, 

IA32_PERFEVTSELx

0H

0H

Unchanged

IA32_FIXED_CTRx, 

IA32_FIXED_CTR_CTRL, 
Global Perf Counter Controls

0H

0H

Unchanged

Data and Code Cache, TLBs

Invalid

6

Invalid

6

Unchanged

Fixed MTRRs

Disabled

Disabled

Unchanged

Variable MTRRs

Disabled

Disabled

Unchanged

Machine-Check Banks

Undefined

Undefined

W

Unchanged

Last Branch Record Stack

0

0

W

Unchanged

APIC

Enabled

Enabled

Unchanged

X2APIC

Disabled

Disabled

Unchanged

MSR_FEATURE_CONFIG

0

0

W

Unchanged

IA32_DEBUG_INTERFACE

0

0

W

Unchanged

NOTES: 

1. The 10 most-significant bits of the EFLAGS register are undefined following a reset. Software should not depend on the states of 

any of these bits.

2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared.
3. Where “n” is the Extended Model Value for the respective processor, and “xx” = don’t care.
4. If Built-In Self-Test (BIST) is invoked on power up or reset, EAX is 0 only if all tests passed. (BIST cannot be invoked during an INIT.)
5. The state of the x87 FPU and MMX registers is not changed by the execution of an INIT.
6. Internal caches are invalid after power-up and RESET, but left unchanged with an INIT.
W: Warm RESET behavior differs from power-on RESET with details listed in Table 9-2.

Table 9-2.  Variance of RESET Values in Selected Intel Architecture Processors

State

XREF 

Value

Feature Flag or DisplayFamily_DisplayModel Signatures

Time-Stamp Counter

Warm RESET Unmodified across warm 

Reset

06_2DH, 06_3EH

Machine-Check Banks

Warm RESET IA32_MCi_Status banks are 

unmodified across warm 

Reset

06_2DH, 06_3EH, 06_3FH, 06_4FH, 06_56H

Last Branch Record Stack Warm RESET LBR stack MSRs are 

unmodified across warm 

Reset

06_1AH, 06_1CH, DisplayFamiy= 06 and DisplayModel >1DH

MSR_FEATURE_CONFIG

Warm RESET Unmodified across warm 

Reset

06_2AH, 06_2CH, 06_2DH, 06_2FH, 06_3AH, 

DisplayFamiy= 06 and DisplayModel >37H

Intel Processor Trace 

MSRs

Warm RESET Clears 

IA32_RTIT_CTL.TraceEn, 

the rest of MSRs are 

unmodified

If CPUID.(EAX=14H, ECX=0H):EBX[bit 2] = 1

IA32_DEBUG_INTERFACE Warm RESET Unmodified across warm 

Reset

If CPUID.01H:ECX.[11] = 1 

Table 9-1.  IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT  (Contd.)

Register

Power up

Reset

INIT