Vol. 3A 8-21

MULTIPLE-PROCESSOR MANAGEMENT

1. Initializes memory.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs.
4. Enables the caches.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads the EBX, ECX, and EDX 

registers to determine if the BSP is “GenuineIntel.”

6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves the values in the EAX, ECX, 

and EDX registers in a system configuration space in RAM for use later.

7. Loads start-up code for the AP to execute into a 4-KByte page in the lower 1 MByte of memory.
8. Switches to protected mode and ensures that the APIC address space is mapped to the strong uncacheable 

(UC) memory type.

9. Determine the BSP’s APIC ID from the local APIC ID register (default is 0), the code snippet below is an 

example that applies to logical processors in a system whose local APIC units operate in xAPIC mode that APIC 
registers are accessed using memory mapped interface:

MOV ESI, APIC_ID; Address of local APIC ID register
MOV EAX, [ESI];
AND EAX, 0FF000000H; Zero out all other bits except APIC ID
MOV BOOT_ID, EAX; Save in memory

Saves the APIC ID in the ACPI and/or MP tables and optionally in the system configuration space in RAM.

10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bit vector. The 8-bit vector 

defines the address of a 4-KByte page in the real-address mode address space (1-MByte space). For example, 
a vector of 0BDH specifies a start-up memory address of 000BD000H. 

11. Enables the local APIC by setting bit 8 of the APIC spurious vector register (SVR).

MOV ESI, SVR; Address of SVR
MOV EAX, [ESI];
OR  EAX, APIC_ENABLED; Set bit 8 to enable (0 on reset)
MOV [ESI], EAX;

12. Sets up the LVT error handling entry by establishing an 8-bit vector for the APIC error handler.

MOV ESI, LVT3;
MOV EAX, [ESI];
AND EAX, FFFFFF00H; Clear out previous vector.
OR EAX, 000000xxH; xx is the 8-bit vector the APIC error handler. 
MOV [ESI], EAX;

13. Initializes the Lock Semaphore variable VACANT to 00H. The APs use this semaphore to determine the order in 

which they execute BIOS AP initialization code.

14. Performs the following operation to set up the BSP to detect the presence of APs in the system and the number 

of processors (within a finite duration, minimally 100 milliseconds):
— Sets the value of the COUNT variable to 1.
— In the AP BIOS initialization code, the AP will increment the COUNT variable to indicate its presence. The 

finite duration while waiting for the COUNT to be updated can be accomplished with a timer. When the timer 
expires, the BSP checks the value of the COUNT variable. If the timer expires and the COUNT variable has 
not been incremented, no APs are present or some error has occurred.

15. Broadcasts an INIT-SIPI-SIPI IPI sequence to the APs to wake them up and initialize them. If software knows 

how many logical processors it expects to wake up, it may choose to poll the COUNT variable. If the expected 
processors show up before the 100 millisecond timer expires, the timer can be canceled and skip to step 16. 
The left-hand-side of the procedure illustrated in Table 8-1 provides an algorithm when the expected processor 
count is unknown. The right-hand-side of Table 8-1 can be used when the expected processor count is known.