6-46 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A; see “XSAVE—Save 
Processor Extended States” and “XRSTOR—Restore Processor Extended States” in Chapter 5 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2C).
The MOVDQU, MOVUPS, and MOVUPD instructions perform 128-bit unaligned loads or stores. The LDDQU instruc-
tions loads 128-bit unaligned data. They do not generate general-protection exceptions (#GP) when operands are 
not aligned on a 16-byte boundary. If alignment checking is enabled, alignment-check exceptions (#AC) may or 
may not be generated depending on processor implementation when data addresses are not aligned on an 8-byte 
boundary.
FSAVE and FRSTOR instructions can generate unaligned references, which can cause alignment-check faults. These 
instructions are rarely needed by application programs. 

Exception Error Code

Yes. The error code is null; all bits are clear except possibly bit 0 — EXT; see Section 6.13. EXT is set if the #AC is 
recognized during delivery of an event other than a software interrupt (see “INT n/INTO/INT 3—Call to Interrupt 
Procedure” in Chapter 3 of the Intel

®

64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).

Saved Instruction Pointer

The saved contents of CS and EIP registers point to the instruction that generated the exception.

Program State Change

A program-state change does not accompany an alignment-check fault, because the instruction is not executed.