Vol. 3C 35-305

MODEL-SPECIFIC REGISTERS (MSRS)

1

Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.

2

Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.

3

MCERR# Drive Enable (R/W) 
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.

4

Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.

6: 5

Reserved

7

BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.

8

Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled 

9

Execute BIST (R/O)
1 = Enabled; 0 = Disabled 

10

MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled

11

Reserved

12

BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled 

13

Reserved

14

1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes

15

Reserved

17:16

APIC Cluster ID (R/O)

18

System Bus Frequency (R/O)
0 = 100 MHz
1 = Reserved

19

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

26:22

Clock Frequency Ratio (R/O)

3AH

58

IA32_FEATURE_CONTROL

Unique

Control Features in IA-32 Processor (R/W) 
See Table 35-2.

Table 35-44.  MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV 

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec