35-256 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
23
VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24
Other Log
When set, indicates that the OTHER Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:38
Reserved.
6D0H
1744
MSR_
LASTBRANCH_16_TO_IP
Thread
Last Branch Record 16 To IP (R/W)
One of 32 triplets of last branch record registers on the last branch
record stack. This part of the stack contains pointers to the
destination instruction. See also:
• Last Branch Record Stack TOS at 1C9H
6D1H
1745
MSR_
LASTBRANCH_17_TO_IP
Thread
Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D2H
1746
MSR_
LASTBRANCH_18_TO_IP
Thread
Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D3H
1747
MSR_
LASTBRANCH_19_TO_IP
Thread
Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D4H
1748
MSR_
LASTBRANCH_20_TO_IP
Thread
Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D5H
1749
MSR_
LASTBRANCH_21_TO_IP
Thread
Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D6H
1750
MSR_
LASTBRANCH_22_TO_IP
Thread
Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D7H
1751
MSR_
LASTBRANCH_23_TO_IP
Thread
Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D8H
1752
MSR_
LASTBRANCH_24_TO_IP
Thread
Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec