Vol. 3C 35-245
MODEL-SPECIFIC REGISTERS (MSRS)
55
Thread
Set 1 to clear Trace_ToPA_PMI.
57:56
Reserved.
58
Thread
Set 1 to clear LBR_Frz.
59
Thread
Set 1 to clear CTR_Frz.
60
Thread
Set 1 to clear ASCI.
61
Thread
Set 1 to clear Ovf_Uncore
62
Thread
Set 1 to clear Ovf_BufDSSAVE
63
Thread
Set 1 to clear CondChgd
391H
913
IA32_PERF_GLOBAL_STAT
US_SET
See Table 35-2. See Section 18.2.2.3, “Full-Width Writes to
Performance Counter Registers.â€
0
Thread
Set 1 to cause Ovf_PMC0 = 1
1
Thread
Set 1 to cause Ovf_PMC1 = 1
2
Thread
Set 1 to cause Ovf_PMC2 = 1
3
Thread
Set 1 to cause Ovf_PMC3 = 1
4
Thread
Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4)
5
Thread
Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5)
6
Thread
Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6)
7
Thread
Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7)
31:8
Reserved.
32
Thread
Set 1 to cause Ovf_FixedCtr0 = 1
33
Thread
Set 1 to cause Ovf_FixedCtr1 = 1
34
Thread
Set 1 to cause Ovf_FixedCtr2 = 1
54:35
Reserved.
55
Thread
Set 1 to cause Trace_ToPA_PMI = 1
57:56
Reserved.
58
Thread
Set 1 to cause LBR_Frz = 1
59
Thread
Set 1 to cause CTR_Frz = 1
60
Thread
Set 1 to cause ASCI = 1
61
Thread
Set 1 to cause Ovf_Uncore
62
Thread
Set 1 to cause Ovf_BufDSSAVE
63
Reserved.
392H
913
IA32_PERF_GLOBAL_INUSE
3F7H
1015
MSR_PEBS_FRONTEND
Thread
FrontEnd Precise Event Condition Select (R/W)
2:0
Event Code Select
3
Reserved.
4
Event Code Select High
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec