35-244 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
0
Thread
Ovf_PMC0
1
Thread
Ovf_PMC1
2
Thread
Ovf_PMC2
3
Thread
Ovf_PMC3
4
Thread
Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5
Thread
Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Thread
Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7
Thread
Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
31:8
Reserved.
32
Thread
Ovf_FixedCtr0
33
Thread
Ovf_FixedCtr1
34
Thread
Ovf_FixedCtr2
54:35
Reserved.
55
Thread
Trace_ToPA_PMI.
57:56
Reserved.
58
Thread
LBR_Frz.
59
Thread
CTR_Frz.
60
Thread
ASCI.
61
Thread
Ovf_Uncore
62
Thread
Ovf_BufDSSAVE
63
Thread
CondChgd
390H
912
IA32_PERF_GLOBAL_STAT
US_RESET
See Table 35-2. See Section 18.2.2.3, “Full-Width Writes to
Performance Counter Registers.â€
0
Thread
Set 1 to clear Ovf_PMC0
1
Thread
Set 1 to clear Ovf_PMC1
2
Thread
Set 1 to clear Ovf_PMC2
3
Thread
Set 1 to clear Ovf_PMC3
4
Thread
Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5
Thread
Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Thread
Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7
Thread
Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
31:8
Reserved.
32
Thread
Set 1 to clear Ovf_FixedCtr0
33
Thread
Set 1 to clear Ovf_FixedCtr1
34
Thread
Set 1 to clear Ovf_FixedCtr2
54:35
Reserved.
Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake
Microarchitecture
Register
Address
Register Name
Scope
Bit Description
Hex
Dec