35-184 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

9

MCG_EXT_P

10

MCP_CMCI_P

11

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

24

MCG_SER_P

63:25

Reserved.

17AH

378

IA32_MCG_STATUS

Thread

(R/W0)

0

RIPV

1

EIPV

2

MCIP

3

LMCE signaled

63:4

Reserved.

1AEH

430

MSR_TURBO_RATIO_LIMIT1 Package

Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1

7:0

Package

Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active. 

15:8

Package

Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10core active. 

23:16

Package

Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.

31:24

Package

Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.

39:32

Package

Maximum Ratio Limit for 13C
Maximum turbo ratio limit of 13 core active.

47:40

Package

Maximum Ratio Limit for 14C
Maximum turbo ratio limit of 14 core active.

55:48

Package

Maximum Ratio Limit for 15C
Maximum turbo ratio limit of 15 core active.

62:56

Reserved

63

Package

Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration

1

 specified in 

MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).

29DH

669

IA32_MC29_CTL2

Package

See Table 35-2.

29EH

670

IA32_MC30_CTL2

Package

See Table 35-2.

29FH

671

IA32_MC31_CTL2

Package

See Table 35-2.

Table 35-25.  Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel 

Signature 06_3EH

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec