Vol. 3A 4-39

PAGING

— The processor does not create a PDPTE-cache entry unless the P flag is 1, the PS flag is 0, and the reserved 

bits are 0 in the PML4E and the PDPTE in memory.

— The processor does not create a PDPTE-cache entry unless the accessed flags are 1 in the PML4E and the 

PDPTE in memory; before caching a translation, the processor sets any accessed flags that are not already 
1.

— The processor may create a PDPTE-cache entry even if there are no translations for any linear address that 

might use that entry.

— If the processor creates a PDPTE-cache entry, the processor may retain it unmodified even if software 

subsequently modifies the corresponding PML4E or PDPTE in memory.

•

PDE cache. The use of the PDE cache depends on the paging mode:
— For 32-bit paging, each PDE-cache entry is referenced by a 10-bit value and is used for linear addresses for 

which bits 31:22 have that value.

— For PAE paging, each PDE-cache entry is referenced by an 11-bit value and is used for linear addresses for 

which bits 31:21 have that value.

— For IA-32e paging, each PDE-cache entry is referenced by a 27-bit value and is used for linear addresses 

for which bits 47:21 have that value.

A PDE-cache entry contains information from the PML4E, PDPTE, and PDE used to translate the relevant linear 
addresses (for 32-bit paging and PAE paging, only the PDE applies):
— The physical address from the PDE (the address of the page table). (No PDE-cache entry is created for a 

PDE that maps a page.)

— The logical-AND of the R/W flags in the PML4E, PDPTE, and PDE.
— The logical-AND of the U/S flags in the PML4E, PDPTE, and PDE.
— The logical-OR of the XD flags in the PML4E, PDPTE, and PDE.
— The values of the PCD and PWT flags of the PDE.
The following items detail how a processor may use the PDE cache (references below to PML4Es and PDPTEs 
apply only to IA-32e paging):
— If the processor has a PDE-cache entry for a linear address, it may use that entry when translating the 

linear address (instead of the PML4E, the PDPTE, and the PDE in memory).

— The processor does not create a PDE-cache entry unless the P flag is 1, the PS flag is 0, and the reserved 

bits are 0 in the PML4E, the PDPTE, and the PDE in memory.

— The processor does not create a PDE-cache entry unless the accessed flag is 1 in the PML4E, the PDPTE, 

and the PDE in memory; before caching a translation, the processor sets any accessed flags that are not 
already 1.

— The processor may create a PDE-cache entry even if there are no translations for any linear address that 

might use that entry.

— If the processor creates a PDE-cache entry, the processor may retain it unmodified even if software subse-

quently modifies the corresponding PML4E, the PDPTE, or the PDE in memory.

Information from a paging-structure entry can be included in entries in the paging-structure caches for other 
paging-structure entries referenced by the original entry. For example, if the R/W flag is 0 in a PML4E, then the R/W 
flag will be 0 in any PDPTE-cache entry for a PDPTE from the page-directory-pointer table referenced by that 
PML4E. This is because the R/W flag of each such PDPTE-cache entry is the logical-AND of the R/W flags in the 
appropriate PML4E and PDPTE.
The paging-structure caches contain information only from paging-structure entries that reference other paging 
structures (and not those that map pages). Because the G flag is not used in such paging-structure entries, the 
global-page feature does not affect the behavior of the paging-structure caches.
The processor may create entries in paging-structure caches for translations required for prefetches and for 
accesses that are a result of speculative execution that would never actually occur in the executed code path.
As noted in Section 4.10.1, any entries created in paging-structure caches by a logical processor are associated 
with the current PCID.