35-148 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

8

Thermal threshold #2 status (RO) 
See Table 35-2.

9

Thermal threshold #2 log (R/WC0) 
See Table 35-2.

10

Power Limitation status (RO) 
See Table 35-2.

11

Power Limitation log (R/WC0) 
See Table 35-2.

15:12

Reserved.

22:16

Digital Readout (RO) 
See Table 35-2.

26:23

Reserved.

30:27

Resolution in degrees Celsius (RO) 
See Table 35-2.

31

Reading Valid (RO) 
See Table 35-2.

63:32

Reserved.

1A0H

416

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W) 
Allows a variety of processor functions to be enabled and disabled.

0

Thread

Fast-Strings Enable 
See Table 35-2

6:1

Reserved.

7

Thread

Performance Monitoring Available (R) 
See Table 35-2.

10:8

Reserved.

11

Thread

Branch Trace Storage Unavailable (RO) 
See Table 35-2.

12

Thread

Processor Event Based Sampling Unavailable (RO) 
See Table 35-2.

15:13

Reserved.

16

Package

Enhanced Intel SpeedStep Technology Enable (R/W) 
See Table 35-2.

18

Thread

ENABLE MONITOR FSM. (R/W) See Table 35-2.

21:19

Reserved.

22

Thread

Limit CPUID Maxval (R/W) 
See Table 35-2.

23

Thread

xTPR Message Disable (R/W) 
See Table 35-2.

Table 35-18.  MSRs Supported by Intel® Processors 

based on Intel® microarchitecture code name Sandy Bridge (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec