35-146 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instruction can be mis-configured
if a privileged agent unintentionally writes 11b.
63:2
Reserved.
174H
372
IA32_SYSENTER_CS
Thread
175H
373
IA32_SYSENTER_ESP
Thread
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Thread
See Table 35-2.
179H
377
IA32_MCG_CAP
Thread
17AH
378
IA32_MCG_STATUS
Thread
0
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted.
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
Reserved.
186H
390
IA32_
PERFEVTSEL0
Thread
187H
391
IA32_
PERFEVTSEL1
Thread
188H
392
IA32_
PERFEVTSEL2
Thread
189H
393
IA32_
PERFEVTSEL3
Thread
18AH
394
IA32_
PERFEVTSEL4
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
18BH
395
IA32_
PERFEVTSEL5
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
18CH
396
IA32_
PERFEVTSEL6
Core
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
Table 35-18. MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec