35-112 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

34

Thread

XD Bit Disable (R/W)
See Table 35-2.

37:35

Reserved.

38

Package

Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost 

Technology, the turbo mode feature is disabled and the IDA_Enable 

feature flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: 

EAX[1] reports the processor’s support of turbo mode is enabled.
Note: the power-on default value is used by BIOS to detect 

hardware support of turbo mode. If power-on default value is 1, 

turbo mode is available in the processor. If power-on default value 

is 0, turbo mode is not available.

63:39

Reserved.

1A2H

418

MSR_

TEMPERATURE_TARGET

Thread

15:0

Reserved.

23:16

Temperature Target (R) 
The minimum temperature at which PROCHOT# will be asserted. 

The value is degree C.

63:24

Reserved.

1A4H

420

MSR_MISC_FEATURE_

CONTROL

Miscellaneous Feature Control (R/W) 

0

Core

L2 Hardware Prefetcher Disable (R/W) 
If 1, disables the L2 hardware prefetcher, which fetches additional 

lines of code or data into the L2 cache.

1

Core

L2 Adjacent Cache Line Prefetcher Disable (R/W) 
If 1, disables the adjacent cache line prefetcher, which fetches the 

cache line that comprises a cache line pair (128 bytes).

2

Core

DCU Hardware Prefetcher Disable (R/W) 
If 1, disables the L1 data cache prefetcher, which fetches the next 

cache line into L1 data cache.

3

Core

DCU IP Prefetcher Disable (R/W) 
If 1, disables the L1 data cache IP prefetcher, which uses 

sequential load history (based on instruction Pointer of previous 

loads) to determine whether to prefetch additional lines.

63:4

Reserved.

1A6H

422

MSR_OFFCORE_RSP_0

Thread

Offcore Response Event Select Register (R/W)

1AAH

426

MSR_MISC_PWR_MGMT

See http://biosbits.org.

Table 35-13.  MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec