Vol. 3C 35-111
MODEL-SPECIFIC REGISTERS (MSRS)
19AH
410
IA32_CLOCK_MODULATION Thread
Clock Modulation (R/W)
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
0
Reserved.
3:1
On demand Clock Modulation Duty Cycle (R/W)
4
On demand Clock Modulation Enable (R/W)
63:5
Reserved.
19BH
411
IA32_THERM_INTERRUPT
Core
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Core
Thermal Monitor Status (R/W)
See Table 35-2.
1A0H
416
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0
Thread
Fast-Strings Enable
See Table 35-2.
2:1
Reserved.
3
Thread
Automatic Thermal Control Circuit Enable (R/W)
See Table 35-2. Default value is 1.
6:4
Reserved.
7
Thread
Performance Monitoring Available (R)
See Table 35-2.
10:8
Reserved.
11
Thread
Branch Trace Storage Unavailable (RO)
See Table 35-2.
12
Thread
Processor Event Based Sampling Unavailable (RO)
See Table 35-2.
15:13
Reserved.
16
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 35-2.
18
Thread
ENABLE MONITOR FSM. (R/W) See Table 35-2.
21:19
Reserved.
22
Thread
Limit CPUID Maxval (R/W)
See Table 35-2.
23
Thread
xTPR Message Disable (R/W)
See Table 35-2.
33:24
Reserved.
Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address
Register Name
Scope
Bit Description
Hex
Dec