Vol. 3C 35-97
MODEL-SPECIFIC REGISTERS (MSRS)
60AH
1546
MSR_PKGC3_IRTL
Package
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-
States.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C3 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings.
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
Reserved.
60BH
1547
MSR_PKGC_IRTL1
Package
Package C6/C7S Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit used by the
processor to manage transition to package C6 or C7S state.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-
States.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C6 or C7S state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings
14:13
Reserved.
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used
by the processor for package C-sate management.
63:16
Reserved.
60CH
1548
MSR_PKGC_IRTL2
Package
Package C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit used by the
processor to manage transition to package C7 state.
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-
States.
9:0
Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package
should be put into a package C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response
time limit. See Table 35-18 for supported time unit encodings
Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
Address
Register Name
Scope
Bit Description
Hex
Dec