Vol. 3C 35-79

MODEL-SPECIFIC REGISTERS (MSRS)

7

Core

Performance Monitoring Available (R) 
See Table 35-2.

10:8

Reserved.

11

Core

Branch Trace Storage Unavailable (RO) 
See Table 35-2.

12

Core

Processor Event Based Sampling Unavailable (RO) 
See Table 35-2.

15:13

Reserved.

16

Module

Enhanced Intel SpeedStep Technology Enable (R/W) 
See Table 35-2.

18

Core

ENABLE MONITOR FSM (R/W) 
See Table 35-2.

21:19

Reserved.

22

Core

Limit CPUID Maxval (R/W) 
See Table 35-2.

23

Module

xTPR Message Disable (R/W) 
See Table 35-2.

33:24

Reserved.

34

Core

XD Bit Disable (R/W) 
See Table 35-2.

37:35

Reserved.

38

Module

Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost 

Technology, the turbo mode feature is disabled and the IDA_Enable 

feature flag will be clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: 

EAX[1] reports the processor’s support of turbo mode is enabled.
Note: the power-on default value is used by BIOS to detect 

hardware support of turbo mode. If power-on default value is 1, 

turbo mode is available in the processor. If power-on default value 

is 0, turbo mode is not available.

63:39

Reserved.

1C8H

456

MSR_LBR_SELECT

Core

Last Branch Record Filtering Select Register (R/W) 
See Section 17.7.2, “Filtering of Last Branch Records.”

0

CPL_EQ_0

1

CPL_NEQ_0

2

JCC

3

NEAR_REL_CALL

4

NEAR_IND_CALL

5

NEAR_RET

Table 35-7.  MSRs Common to the Silvermont and Airmont Microarchitectures 

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec