35-70 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

174H

372

IA32_SYSENTER_CS

Core

See Table 35-2.

175H

373

IA32_SYSENTER_ESP

Core

See Table 35-2.

176H

374

IA32_SYSENTER_EIP

Core

See Table 35-2.

179H

377

IA32_MCG_CAP

Core

See Table 35-2.

17AH

378

IA32_MCG_STATUS

Core

0

RIPV
When set, bit indicates that the instruction addressed by the 

instruction pointer pushed on the stack (when the machine check 

was generated) can be used to restart the program. If cleared, the 

program cannot be reliably restarted

1

EIPV
When set, bit indicates that the instruction addressed by the 

instruction pointer pushed on the stack (when the machine check 

was generated) is directly associated with the error.

2

MCIP
When set, bit indicates that a machine check has been generated. If 

a second machine check is detected while this bit is still set, the 

processor enters a shutdown state. Software should write this bit 

to 0 after processing a machine check exception.

63:3

Reserved.

186H

390

IA32_PERFEVTSEL0

Core

See Table 35-2.

7:0

Event Select

15:8

UMask

16

USR

17

OS

18

Edge

19

PC

20

INT

21

Reserved

22

EN

23

INV

31:24

CMASK

63:32

Reserved.

187H

391

IA32_PERFEVTSEL1

Core

See Table 35-2.

198H

408

IA32_PERF_STATUS

Module

See Table 35-2.

199H

409

IA32_PERF_CTL

Core

See Table 35-2.

19AH

410

IA32_CLOCK_MODULATION Core

Clock Modulation (R/W) 
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named 

IA32_THERM_CONTROL MSR.

Table 35-6.   MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom 

Processors

Address

Register Name

Scope

Bit Description

 Hex

Dec