Vol. 3C 35-61
MODEL-SPECIFIC REGISTERS (MSRS)
176H
374
IA32_SYSENTER_EIP
Unique
See Table 35-2.
179H
377
IA32_MCG_CAP
Unique
17AH
378
IA32_MCG_STATUS
Unique
0
RIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) can be used to restart the program. If cleared, the
program cannot be reliably restarted
1
EIPV
When set, bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check
was generated) is directly associated with the error.
2
MCIP
When set, bit indicates that a machine check has been generated. If
a second machine check is detected while this bit is still set, the
processor enters a shutdown state. Software should write this bit
to 0 after processing a machine check exception.
63:3
Reserved.
186H
390
IA32_PERFEVTSEL0
Unique
See Table 35-2.
187H
391
IA32_PERFEVTSEL1
Unique
See Table 35-2.
198H
408
IA32_PERF_STATUS
Shared
198H
408
MSR_PERF_STATUS
Shared
15:0
Current Performance State Value.
39:16
Reserved.
44:40
Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.
63:45
Reserved.
199H
409
IA32_PERF_CTL
Unique
See Table 35-2.
19AH
410
IA32_CLOCK_MODULATION Unique
Clock Modulation (R/W)
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
19BH
411
IA32_THERM_INTERRUPT
Unique
Thermal Interrupt Control (R/W)
See Table 35-2.
19CH
412
IA32_THERM_STATUS
Unique
Thermal Monitor Status (R/W)
See Table 35-2.
19DH
413
MSR_THERM2_CTL
Shared
15:0
Reserved.
Table 35-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec