35-48 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

0

RIPV
When set, bit indicates that the instruction addressed by the 

instruction pointer pushed on the stack (when the machine check 

was generated) can be used to restart the program. If cleared, the 

program cannot be reliably restarted.

1

EIPV
When set, bit indicates that the instruction addressed by the 

instruction pointer pushed on the stack (when the machine check 

was generated) is directly associated with the error.

2

MCIP
When set, bit indicates that a machine check has been generated. If 

a second machine check is detected while this bit is still set, the 

processor enters a shutdown state. Software should write this bit 

to 0 after processing a machine check exception.

63:3

Reserved.

186H

390

IA32_PERFEVTSEL0

Unique

See Table 35-2.

187H

391

IA32_PERFEVTSEL1

Unique

See Table 35-2.

198H

408

IA32_PERF_STATUS

Shared

See Table 35-2.

198H

408

MSR_PERF_STATUS

Shared

15:0

Current Performance State Value.

30:16

Reserved.

31

XE Operation (R/O).
If set, XE operation is enabled. Default is cleared.

39:32

Reserved.

44:40

Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.

45

Reserved.

46

Non-Integer Bus Ratio (R/O)
Indicates non-integer bus ratio is enabled. Applies processors 

based on Enhanced Intel Core microarchitecture.

63:47

Reserved.

199H

409

IA32_PERF_CTL

Unique

See Table 35-2.

19AH

410

IA32_CLOCK_MODULATION Unique

Clock Modulation (R/W) 
See Table 35-2.
IA32_CLOCK_MODULATION MSR was originally named 

IA32_THERM_CONTROL MSR.

19BH

411

IA32_THERM_INTERRUPT

Unique

Thermal Interrupt Control (R/W) 
See Table 35-2.

19CH

412

IA32_THERM_STATUS

Unique

Thermal Monitor Status (R/W) 
See Table 35-2.

Table 35-3.  MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec