Vol. 3C 35-47
MODEL-SPECIFIC REGISTERS (MSRS)
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 110B.
333.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 111B.
63:3
Reserved.
E7H
231
IA32_MPERF
Unique
Maximum Performance Frequency Clock Count (RW)
See Table 35-2.
E8H
232
IA32_APERF
Unique
Actual Performance Frequency Clock Count (RW)
See Table 35-2.
FEH
254
IA32_MTRRCAP
Unique
11
Unique
SMRR Capability Using MSR 0A0H and 0A1H (R)
11EH
281
MSR_BBL_CR_CTL3
Shared
0
L2 Hardware Enabled (RO)
1 = If the L2 is hardware-enabled
0 = Indicates if the L2 is hardware-disabled
7:1
Reserved.
8
L2 Enabled (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved.
23
L2 Not Present (RO)
0 = L2 Present
1 = L2 Not Present
63:24
Reserved.
174H
372
IA32_SYSENTER_CS
Unique
175H
373
IA32_SYSENTER_ESP
Unique
See Table 35-2.
176H
374
IA32_SYSENTER_EIP
Unique
See Table 35-2.
179H
377
IA32_MCG_CAP
Unique
17AH
378
IA32_MCG_STATUS
Unique
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register
Address
Register Name
Shared/
Unique
Bit Description
Hex
Dec