Vol. 3A 4-15
PAGING
— Bits 11:3 are bits 20:12 of the linear address.
— Bits 2:0 are 0.
•
Because a PTE is identified using bits 31:12 of the linear address, every PTE maps a 4-KByte page (see
Table 4-11). The final physical address is computed as follows:
— Bits 51:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If the P flag (bit 0) of a PDE or a PTE is 0 or if a PDE or a PTE sets any reserved bit, the entry is used neither to
reference another paging-structure entry nor to map a page. There is no translation for a linear address whose
translation would use such a paging-structure entry; a reference to such a linear address causes a page-fault
exception (see Section 4.7).
The following bits are reserved with PAE paging:
•
If the P flag (bit 0) of a PDE or a PTE is 1, bits 62:MAXPHYADDR are reserved.
•
If the P flag and the PS flag (bit 7) of a PDE are both 1, bits 20:13 are reserved.
•
If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserved.
•
If the PAT is not supported:
1
— If the P flag of a PTE is 1, bit 7 is reserved.
— If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.
A reference using a linear address that is successfully translated to a physical address is performed only if allowed
by the access rights of the translation; see Section 4.6.
1. See Section 4.1.4 for how to determine whether the PAT is supported.
Figure 4-5. Linear-Address Translation to a 4-KByte Page using PAE Paging
0
Directory
Table
Offset
Page Directory
PDE with PS=0
Page Table
PTE
4-KByte Page
Physical Address
31
20
11
12
21
Linear Address
PDPTE value
30 29
PDPTE Registers
Directory Pointer
2
9
12
9
40
40
40